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| ht45r37 tinypower tm c/r-f type 8-bit otp mcu rev. 1.20 1 february 25, 2011 general description the ht45r37 is a tinypower tm c/r to f type 8-bit high performance risc architecture microcontroller. as a c/r to f type of mcu, the device can interface to 16 external c or r type sensors and convert their values to a fre - quency value for processing. in addition its internal a/d converter allows the device to interface directly to analog signals and its integrated dual channel pulse width modu - lators allows control of external motors, leds etc. with their fully integrated spi and i 2 c functions, design - ers are provided with a means of easy communication with external peripheral hardware. the benefits of inte - grated a/d, c/r to f converter, and pwm functions, in addition to low power consumption, high performance, i/o flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appli - ance and industrial application areas. some of these products could include electronic metering, environmen - tal monitoring, handheld instruments, electronically con - trolled tools, motor driving in addition to many others. the unique holtek tinypower technology also gives the devices extremely low current consumption characteris - tics, an extremely important consideration in the present trend for low power battery powered applications. the usual holtek mcu features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applica - tions require a minimum of external components. features operating voltage: f sys =32768hz: 2.2v~5.5v f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.0v~5.5v f sys =12mhz: 4.5v~5.5v otp program memory: 4k 15 ram data memory: 160 8 27 bidirectional i/o lines three external interrupt input shared with i/o lines two 8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler external c/r to f converter 16-channel capacitor/resistor sensor inputs integrated crystal, irc, erc and rtc oscillator fully integrated internal rc oscillator available with three frequencies: 4mhz, 8mhz or 12mhz watchdog timer function lirc or rtc oscillator function for watchdog timer pfd and buzzer for audio frequency generation dual serial interfaces: spi and i 2 c 4 operating modes: normal, slow, idle and sleep 6-level subroutine nesting 6-channel 12-bit resolution a/d converter 2-channel 12-bit pwm output shared with i/o line low voltage reset function - 2.1v, 3.15v, 4.2v low voltage detect function - 2.2v, 3.3v, 4.4v bit manipulation instruction 15-bit table read instructions 63 powerful instructions up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v all instructions executed in one or two machine cycles idle/sleep mode and wake-up functions to reduce power consumption time-base and rtc interrupt 20-pin dip/sop, 24/28-pin skdip/sop/ssop, 32-pin qfn and 44-pin qfp packages technical document tools information faqs application note ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment ht45r37 rev. 1.20 2 february 25, 2011 ! " # $ % & ' # ( ) * ' ( + , - . # # - $ % & ( ! " # + - / 0 # ' 1 0 / 2 # ' 1 2 / 3 # ' 1 3 . # . 4 # 4 & ( ( # ' & ( ( 5 # ! ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 ( 4 # 4 # 9 . 5 4 9 4 4 6 4 7 4 3 4 2 4 0 4 . 4 4 4 . 0 2 3 7 6 9 4 5 / 4 # ' 1 4 / 5 # ' 1 5 & # ' & ! + ! + # 1 ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . ' 0 # + ( # 0 / . # ' 1 . / 0 # ' 1 0 . # . 4 # 4 & ( ( # ' & ( ( 5 # ! ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 . 2 . 0 . . . 4 . 5 4 9 4 4 6 4 7 4 3 4 2 4 0 4 . 0 2 3 7 6 9 4 5 4 4 4 . / . # ' 1 . / 4 # ' 1 4 / 5 # ' 1 5 & # ' & ! + ! + # 1 ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . ' 0 # + ( # 0 ( 5 # 5 # . # . 4 # 4 & ( ( # ' & ( ( 5 # ! ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 4 . 0 2 3 7 6 9 4 5 4 4 4 . 4 0 4 2 4 3 4 7 4 6 4 4 9 . 5 . 4 . . . 0 . 2 . 3. 7. 6. . 90 50 40 . ( 6 # $ 8 # 4 3 ( 7 # 1 # 4 2 ( 3 # 4 0 ( 2 # 4 . ( 0 # 4 4 ( . # 4 5 ( 4 # 4 # 9 ( 5 # 5 # 2 # 2 0 # 0 / 3 # ' 1 3 / 2 # ' 1 2 / 0 # ' 1 0 / . # ' 1 . / 4 # ' 1 4 / 5 # ' 1 5 & # ' & ! + ! + # 1 ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . ' 0 # + ( # 0 / 4 # ' 1 4 0 # 0 2 # 2 . # . 4 # 4 & ( ( # ' & ( ( 5 # ! ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 ( 6 # $ 8 # 4 3 ( 7 # 1 # 4 2 ( 3 # 4 0 . . 6 . 7 . 3 . 2 . 0 . . . 4 . 5 4 9 4 4 6 4 7 4 3 4 . 0 2 3 7 6 9 4 5 4 4 4 . 4 0 4 2 / 5 # ' 1 5 & # ' & ! + ! + # 1 ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . ' 0 # + ( # 0 ( 5 # 5 # ( 4 # 4 # 9 ( . # 4 5 ( 0 # 4 4 ( 2 # 4 . / 2 # ' 1 2 / 3 # ' 1 3 0 # 0 2 # 2 . # . 4 # 4 & ( ( # ' & ( ( 5 # ! ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 ( 6 # $ 8 # 4 3 ( 7 # 1 # 4 2 . . 6 . 7 . 3 . 2 . 0 . . . 4 . 5 4 9 4 4 6 4 7 4 3 4 . 0 2 3 7 6 9 4 5 4 4 4 . 4 0 4 2 / 0 # ' 1 0 / . # ' 1 . / 4 # ' 1 4 / 5 # ' 1 5 & # ' & ! + ! + # 1 ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . ' 0 # + ( # 0 ( 5 # 5 # ( 4 # 4 # 9 & ( ( 5 # ! 1 1 1 1 1 1 1 ' 6 # 1 4 # ( # 6 ' 7 # 1 5 # ( # ( ' # 7 4 . 0 2 3 7 6 9 4 5 4 4 4 . 4 0 4 2 4 3 4 7 4 6 4 4 9 . 5 . 4 . . . 0 . 2 . 3 . 7 . 6 . . 9 0 5 0 4 0 . 0 0 0 20 30 70 60 0 92 52 42 .2 02 2 1 4 # 4 . # . 2 # 2 0 # 0 / 3 # ' 1 3 / 2 # ' 1 2 / 0 # ' 1 0 / . # ' 1 . / 4 # ' 1 4 / 5 # ' 1 5 & ! + ! + ! + # ' 5 # / : # 5 ' 4 # / : # 4 ' . # 5 # . 1 1 1 1 ' 3 # 8 # $ # 3 ' 2 # 4 # # 2 ( 6 # $ 8 # 4 3 ( 7 # 1 # 4 2 ( 3 # 4 0 ( 2 # 4 . ( 0 # 4 4 ( . # 4 5 ( 4 # 4 # 9 ( 5 # 5 # ' 0 # + ( # 0 pin description pin name i/o configuration option description pa0/bz/rc0 pa1/bz /rc1 pa2/tmr0/rc2 pa3/pfd/rc3 pa4/tmr1/scs /rc4 pa5/sck/scl/rc5 pa6/int0/sdi/sda/rc6 pa7/int1/sdo/rc7 i/o sim bz/bz pfd rc0~rc7 bidirectional 8-bit input/output port. each individual bit on this port can be configured as a wake-up input using the pawu register. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull high resistor can be connected to each pin using the papu register. pins pa0, pa1, pa3, pa2, pa4, pa6 and pa7 are shared with bz, bz , pfd, tmr0, tmr1, int0 and int1 respectively. pa7 is also pin-shared with the spi bus data output line, sdo. pa6 is also pin-shared with the spi bus data line, sdi and the i 2 c bus data line sda. pa5 is also pin-shared with the spi bus clock line, sck, and the i 2 c bus clock line scl. pa4 is also pin-shared with the spi bus select line, scs . the c/r to f converter inputs rc0~rc7 are shared with pins pins pa0~pa7 respectively. pb0/an0~pb5/an5 i/o bidirectional 6-bit input/output port. software instructions deter - mine if the pin is a cmos output or schmitt trigger input. a pull high resistor can be connected to each pin using the pbpu regis - ter. pb is pin-shared with the a/d input pins. the a/d inputs are se - lected via software instructions. once selected as an a/d input, the i/o function and pull-high resistor selections are disabled auto - matically. pc0/res i/o pc0 or res bidirectional line i/o. software instructions determine if the pin is an nmos output or schmitt trigger input. a configuration option determines if the pin is to be used as a res pin or as an i/o pin. this pin does not have an internal pull-high function. pd0/pwm0/rc8 pd1/pwm1/rc9 pd2/rc10~pd5/rc13 pd6/pint /rc14 pd7/pclk/rc15 i/o rc8~rc15 bidirectional 8-bit input/output port. software instructions deter- mine if the pin is a cmos output or schmitt trigger input. a pull high resistor can be connected to each pin using the pdpu regis- ter. the pwm outputs, pwm0 and pwm1, are pin shared with pins pd0 and pd1, the function of which is chosen using the pwm reg- isters. pd6 is pin-shared with the peripheral interrupt line, pint . pd7 is pin-shared with the peripheral clock line, pclk. the c/r to f converter inputs rc8~rc15 are shared with pins pins pd0~pd7 respectively. rcout/in i capacitor or resistor connection pin to rc osc/ oscillation input. rref i reference resistor connection pin cref i reference capacitor connection pin pc1/osc1 pc2/osc2 i/o 1.int. rc osc 2.crystal osc 3.ext. rc osc bidirectional 2-line i/o. software instructions determine if the pins are cmos outputs or schmitt trigger inputs. a pull high resistor can be connected to each pin using the pcpu register. configura - tion options determine if the pins are to be used as oscillator pins or i/o pins. configuration options also determine which oscillator mode is selected. the three oscillator modes are: 1. internal rc osc: both pins configured as i/os. 2. external crystal osc: both pins configured as osc1/osc2. 3. external rc osc+pc2: pc1 is configured as osc1 pin, pc2 configured as an i/o. if the internal rc osc is selected, the frequency will be fixed at either 4mhz, 8mhz or 12mhz, dependent upon which configuration option is chosen. ht45r37 rev. 1.20 3 february 25, 2011 pin name i/o configuration option description pc3/osc3 pc4/osc4 i/o rtc osc bidirectional 2-line i/o. software instructions determine if the pins are cmos outputs or schmitt trigger inputs. a pull high resistor can be connected to each pin using the pcpu register. configura - tion options determine if the pins are to be used as oscillator pins or i/o pins. if configuration options select oscillator pins, the pins are connected to a 32768hz crystal oscillator. vdd /avdd positive power supply/analog positive power supply. vss / avss negative power supply, ground/analog negative power supply, ground note: the pin description table represents the largest package available, therefore some of the pins and functions may not be available on smaller package types. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ................................................................80ma i oh total.............................................................. 80ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.0 5.5 v f sys =12mhz 4.5 5.5 v av dd a/d operating voltage 2.7 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =f m =1mhz 170 250 a 5v 380 700 a i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =f m =2mhz 240 360 a 5v 490 800 a i dd3 operating current (crystal osc, rc osc) 3v no load, f sys =f m =4mhz (note 4) 440 660 a 5v 900 1350 a i dd4 operating current (ec mode, filter on) 3v no load, f sys =f m =4mhz 380 570 a 5v 720 1080 a i dd5 operating current (crystal osc, rc osc) 5v no load, f sys =f m =8mhz 1.8 2.7 ma i dd6 operating current (crystal osc, rc osc) 5v no load, f sys =f m =12mhz 2.6 4.0 ma i dd7 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =500khz 150 220 a 5v 340 510 a ht45r37 rev. 1.20 4 february 25, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions i dd8 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =1mhz 180 270 a 5v 400 600 a i dd9 operating current (slow mode, f m =4mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =2mhz 270 400 a 5v 560 840 a i dd10 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =1mhz 240 360 a 5v 540 810 a i dd11 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =2mhz 320 480 a 5v 680 1020 a i dd12 operating current (slow mode, f m =8mhz) (crystal osc, rc osc) 3v no load, f sys =f slow =4mhz 500 750 a 5v 1000 1500 a i dd13 operating current (f sys =32768hz (note 1) or 32k_int internal rc osc) 3v no load, wdt off 816 a 5v 15 30 a i stb1 standby current ( sleep) (f sys ,f sub ,f s ,f wdt =off) 3v no load, system halt, wd off 1 a 5v 2 a i stb2 standby current ( sleep) (f sys ,f wdt =f sub =32768hz (note 1) or 32k_int rc osc) 3v no load, system halt, wdt on 24 a 5v 46 a i stb3 standby current ( idle) (f sys ,f wdt =off; f s =f sub =32768hz (note 1) or 32k_int rc osc) 3v no load, system halt, wdt off 24 a 5v 46 a i stb4 standby current ( idle) (f sys =on, f sys =f m =4mhz, f wdt =off, f s (note 3)= f sub =32768hz (note 1) or 32k_int rc osc) 3v no load, system halt, wdt off, spi or i 2 c on, pclk on, pclk=f sys /8 150 250 a 5v 350 550 a v il1 input low voltage for i/o ports, tmr and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage configuration option: 2.1v 1.98 2.1 2.22 v configuration option: 3.15v 2.98 3.15 3.32 v configuration option: 4.2v 3.98 4.2 4.42 v v lvd low voltage detector voltage configuration option: 2.2v 2.08 2.2 2.32 v configuration option: 3.3v 3.12 3.3 3.50 v configuration option: 4.4v 4.12 4.4 4.70 v i ol1 i/o port sink current - except pc0 3v v ol =0.1v dd 612 ma 5v 10 25 ma ht45r37 rev. 1.20 5 february 25, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions i oh1 i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma i ol2 pc0 sink current 3v v ol =0.1v dd 0.8 1.5 ma 5v 2 4 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 av dd v v ref a/d input reference voltage range av dd v dnl a/c differential non-linearity av dd =5v, v ref =a vdd , t ad =0.5s 2 2 lsb inl adc integral non-linearity av dd =5v, v ref =a vdd , t ad =0.5s 4 4 lsb i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma note: 1. 32768hz is in slow start mode (rtcc.4=1) for the d.c. current measurement. 2. f s is the internal clock for buzzer, rtc, time base and wdt. 3. both timer/event counters are off. timer filter is disabled for all test conditions. 4. all peripherals are in off condition if not mentioned at i dd ,i stb tests. ht45r37 rev. 1.20 6 february 25, 2011 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc, erc osc) 2.2v~5.5v 400 4000 khz 3.0v~5.5v 400 8000 khz 4.5v~5.5v 400 12000 khz f sys2 system clock (hirc osc) 5v 2% 4000 +2% khz 5v 2% 8000 +2% khz 5v 2% 12000 +2% khz f sys3 system clock (rtc crystal osc) 2.2v~5.5v 32768 hz f 4mrcosc 4mhz external rc osc 5v external r=150k 2% 4000 +2% khz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency (tmr0/tmr1) 2.2v~5.5v 0 4000 khz 3.0v~5.5v 0 8000 khz 4.5v~5.5v 0 12000 khz f rc32k 32k rc period (lirc) 2.2v~5.5v, after trim 28.1 31.25 34.4 s t res external reset low pulse width 1 s t lvr low voltage reset time 0.1 0.4 0.6 ms t sst1 system start-up timer period power-on 1024 t sys * t sst2 system start-up timer period for xtal or rtc oscillator wake-up from power down mode 1024 t sys * t sst3 system start-up timer period for rc or external clock wake-up from power down mode 12 t sys * t int interrupt pulse width 1 s t ad a/d clock period 0.5 s t adc a/d conversion time 16 t ad restd reset delay time 100 ms note: *t sys =1/f sys1 , 1/f sys2 or 1/f sys3 ht45r37 rev. 1.20 7 february 25, 2011 power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht45r37 rev. 1.20 8 february 25, 2011 ht45r37 rev. 1.20 9 february 25, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their in - ternal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, in - crement, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accu - mulator and the alu. certain internal registers are im - plemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in - ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. + ; < = ! " ; < 4 = + ; < > 4 = ! " ; < = + ; < > . = ! " ; < > 4 = > 4 > . * < * = * 4 * . * 0 * 2 system clocking and pipelining + ; 4 ! " ; 4 + ; . + 4 . 0 2 3 7 ( ! $ ' ? @ & ' a b 4 . c d ' $ $ ( ! $ ' ? $ b 4 . c d @ @ 1 ! " ; . + ; 0 + ; 7 ! " ; 7 + ; 6 instruction fetching ht45r37 rev. 1.20 10 february 25, 2011 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short pro - gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. mode program counter bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 000000000000 external interrupt 0 000000000100 external interrupt 1 000000001000 timer/event counter 0 overflow 000000001100 timer/event counter 1 overflow 000000010000 spi/i 2 c interrupt 000000010100 c/r to f converter interrupt 000000010100 time base interrupt 000000011000 rtc interrupt 000000011000 a/d converter interrupt 000000011000 external peripheral interrupt 000000011000 skip program counter + 2 loading pcl pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s11~s0: stack register bits ht45r37 rev. 1.20 11 february 25, 2011 stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the acti - vated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or in - terrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a sub - routine or an interrupt routine, signaled by a return in - struction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in- struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic oper - ations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. for these device the pro - gram memory is an otp type, which means it can be programmed only one time. by using the appropriate programming tools, this otp memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field pro - gramming. structure the program memory has a capacity of 4k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are re- served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the external interrupt 0. if the external interrupt pin receives an active edge, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this vector is used by the external interrupt 1. if the external interrupt pin receives an active edge, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 00ch this internal vector is used by the timer/event coun - ter 0. if a timer/event counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. * $ ) 4 * $ ) . * $ ) 0 * $ ) 7 e * * / e * ht45r37 rev. 1.20 12 february 25, 2011 location 010h this internal vector is used by the timer/event coun- ter 1. if a timer/event counter 1 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 014h this internal vector is used by the multi-function inter- rupt 0. the multi-function interrupt 0 vector is shared by the spi/i 2 c and the c/r to f converter interrupt. when an interrupt signal is generated, the program will jump to this location and begin execution if the in - terrupt is enabled and the stack is not full. location 018h this internal vector is used by the multi-function inter - rupt 1. the multi-function interrupt 1 vector is shared by the real time clock interrupt, time base interrupt, a/d converter interrupt and external peripheral inter - rupt. when a interrupt signal is generated, the pro - gram will jump to this location and begin execution if the interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the following diagram illustrates the addressing/data flow of the look-up table: 5 4 2 c & ! " 1 5 & 5 & # . & a # + ) 5 5 5 c 5 5 2 c 5 5 c 5 5 c 5 4 5 c 5 4 c ! " 1 4 & 4 & / a a ' # ( ) ! " & 1 4 3 + + + c 5 5 c + + c + 5 5 c program memory structure instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m]1111@7@6@5@4@3@2@1@0 table location note: pc11~pc8: current program counter bits @7~@0: table pointer tblp bits c / / $ / $ c e b d c / $ % / ht45r37 rev. 1.20 13 february 25, 2011 table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller . this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k program memory of the ht45r37. the ta - ble pointer is setup here to have an initial value of 06h. this will ensure that the first data read from the data ta - ble will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad - dress of the present page if the tabrdc [m] instruc - tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] in - struction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 : : org f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : ht45r37 rev. 1.20 14 february 25, 2011 data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the data memory is subdivided into two sections, the special purpose data memory and the general pur - pose data memory. the start address of the data mem - ory is the address 00h . the last data memory address is ffh. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of data memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller , are stored. most of the registers are both read and write type but some are protected and are read only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h. - ( ( 5 5 c 7 5 c + + c 3 + c data memory structure note: most of the data memory bits can be directly ma- nipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers mp0 and mp1. 5 5 c 5 4 c 5 . c 5 0 c 5 2 c 5 3 c 5 7 c 5 6 c 5 c 5 9 c 5 ' c 5 / c 5 c 5 ( c 5 ! c 5 + c 4 5 c 4 4 c 4 . c 4 0 c 4 2 c 4 3 c 4 7 c 4 6 c 4 c 4 9 c 4 ' c 4 / c 4 c 4 ( c 4 ! c 4 + c . 5 c . 4 c . . c . 0 c . 2 c . 3 c . 7 c . 6 c . c . 9 c . ' c . / c . c . ( c . ! c . + c 0 5 c 0 4 c 0 . c 0 0 c 0 2 c 0 3 c 0 7 c 0 6 c 0 c 0 9 c 0 ' c 0 / c 0 c 0 ( c 0 ! c 0 + c 2 5 c f 3 c + @ g 5 5 g ' 5 5 ' 4 4 ' $ / $ / $ c ' 1 5 5 5 ' ' / / ( ( 5 $ 5 c 4 $ 4 c 1 4 + 5 + 4 ' 5 ' 4 ' . ' ( $ ' ( c ' ( ' $ 8 ( ' ' / ( 1 ! ( - ! ' c ' $ / c / $ $ 5 $ 4 ( ' # $ . 4 4 @ * % special purpose data memory ht45r37 rev. 1.20 15 february 25, 2011 special function registers to ensure successful operation of the microcontroller , certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control and a/d converter operation. the location of these registers within the data memory begins at the address 00h. any unused data memory locations between these special function registers and the point where the general pur - pose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00h. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal register space, do not actually physically exist as normal registers. the method of indirect addressing for data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointer, mp0 or mp1. as the indirect ad - dressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are pro - vided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. ht45r37 rev. 1.20 16 february 25, 2011 accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro- gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller . with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. ( + & : ' ! " # $ % # & ' % ( ) ' e ' " e : e ) e % e * " + ' ( ' " ( ) ' % % e e 1 a g 5 g 6 5 status register ht45r37 rev. 1.20 17 february 25, 2011 in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control registers these 8-bit registers, known as the intc0, intc1, mfic0, mfic1 and intedge registers, control the op - eration of the external and internal timer/event counter interrupt, time base interrupt, real time clock inter - rupt, a/d converter interrupt, c/r to f converter inter - rupt and spi/i 2 c interrupt. by setting various bits within these registers using standard bit manipulation instruc - tions, the enable/disable function of each interrupt can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to dis - able further interrupt and is set by executing the reti instruction. timer/event counter registers the devices contains two 8-bit timer/event counters. the registers, tmr0 and tmr1 are the locations where the timer values are located. these registers can also be preloaded with fixed data to allow different time intervals to be setup. the 8-bit timer/event counters have an associated control register, tmr0c and tmr1c, which contain the setup information for these timers, determines in what mode the timer is to be used as well as containing the timer on/off control function. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc and pd. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc and pdc, also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the con - trol register must be set high, for an output it must be set low. during program initialization, it is important to first setup the control registers to specify which pins are out - puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us - ing the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control reg - isters during normal program operation is a useful fea - ture of these devices. pulse width modulator registers the devices contain two pulse width modulator outputs each with their own related independent control register pair, known as pwm0l/pwm0h and pwm1l/ pwm1h. the 12-bit contents of each register pair, which defines the duty cycle value for the modulation cycle of the pulse width modulator, along with an enable bit are contained in these register pairs. a/d converter registers adrl, adrh, adcr, acsr the device contains a multiple channel 12-bit a/d con - verter. the correct operation of the a/d requires the use of two data registers and two control registers. the two data registers, a high byte data register known as adrh, and a low byte data register known as adrl, are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. functions such as the a/d enable/disable, a/d channel selection and a/d clock frequency are deter - mined using the two control registers, adcr and acsr. c/r to f converter registers the device contains a 16-channel c/r to f converter. the correct operation of the c/r to f converter requires the use of two 16-bit counters and five control registers. the two 16-bit counters, a high byte register known as tmrah/tmrbh, and a low byte register known as tmral/tmrbl. the channel selection of the c/r to f converter is setup via the ascr0~ascr2 control regis- ters. the configuration of the c/r to f converter is setup via the rcoccr or rcocr control registers. serial interface registers the device contains two serial interfaces, an spi and an i 2 c interface. the simctl0, simctl1, simctl2 and simar are the control registers for the serial interface function while the simdr is the data register for the se - rial interface data. port a wake-up register pawu all pins on port a have a wake-up function enable a low going edge on these pins to wake-up the device when it is in a power down mode. the pins on port a that are used to have a wake-up function are selected using this resister. pull-high resistors papu, pbpu, pcpu, pdpu all i/o pins on ports pa, pb, pc and pd, if setup as in - puts, can be connected to an internal pull-high resistor. the pins which require a pull-high resistor to be con - nected are selected using these registers. ht45r37 rev. 1.20 18 february 25, 2011 register clkmod the device operates using a dual clock system whose mode is controlled using this register. the register con - trols functions such as the clock source, the idle mode enable and the division ratio for the slow clock. miscellaneous register misc the miscellaneous register is used to control two func - tions. the four lower bits are used for the watchdog timer control, while the highest four bits are used to se - lect open drain outputs for pins pa0~pa3. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high selec - tions for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides multiple bidirectional input/output lines labeled with port names pa, pb, pc and pd. these i/o ports are mapped to the data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains un- changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu, pbpu, pcpu and pdpu and are im - plemented using weak pmos transistors. port a wake-up the halt instruction forces the microcontroller into a power down condition which preserves power, a fea - ture that is important for battery and other low-power ap - plications. various methods exist to wake-up the microcontroller , one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into enter - ing a power down condition, the processor will remain in a low-power state until the logic condition of the se - lected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up fea - ture using the pawu register. port a open drain function all i/o pins in the device have cmos structures, how - ever port a pins pa0~pa3 can also be setup as open drain structures. this is implemented using the ode0~ ode3 bits in the misc register. i/o port control registers each i/o port has its own control register known as pac, pbc, pcc and pdc, to control the input/output configu - ration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its asso - ciated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos out - put. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en- hanced by the use of pins that have more than one func- tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. external interrupt inputs the external interrupt pins int0 and int1 are pin-shared with i/o pins. for applications not requiring external interrupt inputs, the pin-shared external inter - rupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the intc0 register must be disabled. external timer clock input the external timer pins tmr0 and tmr1 are pin-shared with i/o pins. to configure them to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set and the pin must also be setup as an input. note that the original i/o function will remain even if the pin is setup to be used as an external timer input. ht45r37 rev. 1.20 19 february 25, 2011 + , 6 ( ! 1 5 5 ( ! 1 4 ! % ' 5 ( 4 @ 5 @ ' 4 ( 4 @ 5 @ ' . ( 4 @ 5 @ ' 0 ( 4 @ 5 @ ( ! 5 ( ! 1 . ( ! 1 0 ( ! 4 ( ! . ( ! 0 pa0~pa3 open drain control misc & ( ( h * * ( ( i 8 ( i 8 / ( / ( ( / # i i ' * c generic input/output structure & ( ( h ( / ( / ( ( / ' # ( ' . f ' 5 ' # ( ) . 4 5 * ' ( i 8 i ( i 8 i c a/d input/output structure ht45r37 rev. 1.20 20 february 25, 2011 pfd output the device contains a pfd function whose single out - put is pin-shared with i/o pin pa3. the output function of this pin is chosen via a configuration option and re - mains fixed after the device is programmed. note that the corresponding bit of the port control register, pac.3, must setup the pin as an output to enable the pfd output. if the pac port control register has setup the pin as an input, then the pin will function as a nor - mal logic input with the usual pull-high selection, even if the pfd configuration option has been selected. pwm outputs the device contains two pwm outputs shared with pins pd0 and pd1. the pwm output functions are chosen via registers. note that the corresponding bit of the port control register, pdc, must setup the pin as an output to enable the pwm output. if the pdc port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pwm registers have enabled the pwm function. a/d inputs the device contains a multi-channel a/d converter in - puts. all of these analog inputs are pin-shared with i/o pins on port b. if these pins are to be used as a/d in - puts and not as normal i/o pins then the corresponding bits in the a/d converter control register, adcr, must be properly set. there are no configuration options as - sociated with the a/d function. if used as i/o pins, then full pull-high resistor register remain, however if used as a/d inputs then any pull-high resistor selections as - sociated with these pins will be automatically discon - nected. i/o pin structures the accompanying diagrams illustrate the internal structures of some i/o pin types. as the exact logical construction of the i/o pin will differ from these draw - ings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac, pbc, pcc and pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa, pb, pc and pd, are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port con- trol register or by programming individual bits in the port control register using the set [m].i and clr [m].i in- structions. note that when using these bit control in- structions, a read-modify-write operation takes place. the microcontroller must first read in the data on the en- tire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. - - , - ' ; 5 a / ; 5 a ( ; 5 4 @ 5 @ ' ; 4 a / ; 4 a ; 4 a ( ; 4 4 @ 5 @ ' ; 6 a / ; 3 a ; 2 a ( ; 6 4 @ 5 @ 6 h 5 5 h 4 h 6 pull-high resistor register papu, pbpu, pcpu, pdpu 4 . 0 2 4 . 0 2 e * ( read/write timing ht45r37 rev. 1.20 21 february 25, 2011 timer/event counters the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out time related functions. the device contains two 8-bit count-up timers. as each timer has three different oper - ating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. the provision of a prescaler to the clock circuitry of the 8-bit timer/event counter also gives added range to this timer. there are two types of registers related to the timer/event counters. the first are the registers that contain the actual value of the timer/event counter and into which an initial value can be preloaded. reading from these registers retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer/event counter is to be used. the timer/event counters can have the their clock configured to come from an internal clock source. in addition, their clock source can also be configured to come from an external timer pin. configuring the timer/event counter input clock source the internal timer s clock can originate from various sources. the system clock source is used when the timer/event counter is in the timer mode or in the pulse width measurement mode. this internal clock source is f sys which is also divided by a prescaler, the division ra- tio of which is conditioned by the timer control register, tmrnc, bits tnpsc0~ tnpsc2. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tmr0 or tmr1 depending upon which timer is used. depending upon the condition of the tne bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer registers tmr0, tmr1 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. these registers are known as tmr0 or tmr1. the value in the timer registers in - creases by one each time an internal clock pulse is re - ceived or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffh for the 8-bit timer, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be imme - diately written into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. timer control registers tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. it is the timer control register together with its corre - sponding timer registers that control the full operation of the timer/event counters. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to en - sure its correct operation, a process that is normally car - ried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding timer control register, which are known as the bit pair tnm1/tnm0, must be set to the re- quired logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, depending upon which timer is used, provides the basic on/off con- trol of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. for tim- ers that have prescalers, bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tne. configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter - rupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control regis - ter must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock, f sys , is used as the inter - nal clock for the timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by ht45r37 rev. 1.20 22 february 25, 2011 # ! ) 1 # ! ) ( / ) e % . 6 . f 5 < 4 # 4 f 4 # 4 . = # ! ) 4 5 e ? + ( ! + + # e e e 8-bit timer/event counter structure (n=0, 1) h + ( 5 + ( 4 e + ( + ( , . ( / - 0 1 6 ! ) ) 4 @ e 5 @ ! 1 5 4 . 5 5 5 5 4 4 4 4 5 . 4 5 4 5 5 4 4 5 5 4 4 5 5 4 5 4 5 4 5 4 4 @ 4 4 @ . 4 @ 2 4 @ 4 @ 4 7 4 @ 0 . 4 @ 7 2 4 @ 4 . # ! ) 4 @ 5 @ 4 5 5 4 4 5 5 4 5 4 ) ) % ) 4 @ a e 5 @ e a 1 a g 5 g timer/event counter control register tmrnc ht45r37 rev. 1.20 23 february 25, 2011 a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon or tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and con - tinue counting. the interrupt can be disabled by ensur - ing that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer pin, is used as the timer/event counter clock source, however it is not di- vided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tne, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 11 in this mode the internal clock, f sys , is used as the inter- nal clock for the timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control reg- ister, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tne, which is bit 3 of the timer control register, is low, once a high to low transi - tion has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the > 4 > . > 1 > 1 > 4 timer mode timing chart > . ! " ! ) > 0 > 4 event counter mode timing chart ht45r37 rev. 1.20 24 february 25, 2011 timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will be- gin counting once a low to high transition has been re- ceived on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is im- portant to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin re- turns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is re - set to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event coun- ter in the pulse width measurement mode, the second is to ensure that the port control register configures the pin as an input. programmable frequency divider pfd the programmable frequency divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. the pfd output is pin-shared with the i/o pin pa3. the pfd function is selected via configuration option, how - ever, if not selected, the pin can operate as a normal i/o pin. the clock source for the pfd circuit can originate from either timer/event counter 0 or timer/event counter 1 overflow signal selected via configuration option. the output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. the timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the pfd output to change state. the timer will then be auto - matically reloaded with the preload register value and continue counting-up. > 4 > . > 0 > 2 ! " 1 % ! j 5 pulse width measure mode timing chart ) e % + ( * ' 0 ( + ( ' 0 pfd output control ht45r37 rev. 1.20 25 february 25, 2011 for the pfd output to function, it is essential that the corre - sponding bit of the port a control register pac bit 3 is setup as an output. if setup as an input the pfd output will not function, however, the pin can still be used as a normal in - put pin. the pfd output will only be activated if bit pa3 is set to 1 . this output data bit is used as the on/off control bit for the pfd output. note that the pfd output will be low if the pa3 output data bit is cleared to 0 . using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre - cise values of frequency can be generated. prescaler bits tnpsc0~tnpsc2 of the control register can be used to define the pre-scaling stages of the internal clock source of the timer/event counter. the timer/event counter overflow signal can be used to generate signals for the pfd and timer interrupt. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of external pins for correct operation. as these pins are shared pins they must be configured cor - rectly to ensure they are setup for use as timer/event counter inputs and not as a normal i/o pins. this is im- plemented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. addi- tionally the port control register must be set high to en- sure that the pin is setup as an input. any pull-high resistor on these pins will remain valid even if the pin is used as a timer/event counter input. timer/event counter pins internal filter the external timer/event counter pins are connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width mea - surements due to adverse noise or spikes on the exter - nal timer/event counter input signal. as this internal filter circuit will consume a limited amount of power, a configuration option is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the in - put signal is high. care must be taken when using the fil - ter on/off configuration option as it will be applied not only to both external timer/event counter pins but also to the external interrupt input pins. individual timer/event counter or external interrupt pins cannot be selected to have a filter on/off function. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller . in this mode when the appropriate timer register is full, the microcontroller will generate an inter - nal interrupt signal directing the program flow to the re - spective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn - chronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring program - mers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly in - itialised before using them for the first time. the associ - ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis - ter must also be correctly set to ensure the timer is prop- erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg- isters are unknown. after the timer has been initialised the timer can be turned on and off by controlling the en- able bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer oper - ation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode. ht45r37 rev. 1.20 26 february 25, 2011 timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are en - abled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 0ch ; timer/event counter 0 interrupt vector jmp tmrint ; jump here when the timer/event counter 0 overflows : org 20h ; main program ;internal timer/event counter 0 interrupt routine tmrint: : ; timer/event counter 0 main program placed here : reti : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a; mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov int0c,a set tmr0c.4 ; start timer/event counter 0 - note mode bits must be previously setup c/r to f converter the c/r to f converter function within the device en- ables external resistance and capacitance to be con- verted into a frequency. with this function the device has a way of measuring external capacitance and resis - tance values and can therefore be used in applications such as touch switches. c/r to f operation the c/r to f function is implemented using an external rc oscillator. a single external reference resistor and external reference capacitor are required to be con - nected as shown. these components and the internal inverter circuits form an oscillator circuit whose fre - quency is dependent upon the value of the external ca - pacitance and resistance. by using two internal 16-bit programmable count-up timers, known as timer a and timer b, the converted frequency value can be mea - sured. the value of the two internal 16-bit programmable count-up counters, known as timer a and timer b, are stored within two pairs of registers, tmral/tmrah and tmrbl/tmrbh registers. two other registers, rcoccr and rcocr control the overall operation of the c/r to f converter. the timer a clock source comes from the system clock or from the system clock/4, determined by the rcom bits in the rcoccr register. this clock source deter- mines the value in the tmral/tmrah registers. the timer b clock source comes from the external rc oscil - lator circuit and therefore determines the value in the tmrbl/tmrbl registers. it is a combination of a fixed frequency clock source driving timer a and a varying frequency clock source driving timer b that enables ex - ternal resistance and capacitance values to be mea - sured. the ovb bit, in the rcocr register, decides whether timer a or timer b overflows. when this happens, the rcocf bit will be set and an external rc oscillation converter interrupt occurs. when the c/r to f converter causes timer a or timer b to overflow, the rcocon bit in the rcoccr register will be reset to zero and the counter will stop counting. writing initial values to the tmral/tmrah and tmrbl/tmrbh registers places a start value into timer a and timer b. note that writing to the low byte registers, tmral and tmrbl, only writes the data into a low byte buffer. however writing to the high byte registers, tmrah and tmrbh, will write both the high byte values and the low byte buffer values directly into the timer a and timer b simultaneously. ht45r37 rev. 1.20 27 february 25, 2011 ' / & / j 4 & / j 5 # + ) 1 # + . 4 * * # 2 1 c/r to f converter , , , 5 5 1 1 a g 5 g e a # % ! # + ) ( e ' * . 4 5 5 5 5 5 4 4 4 4 5 5 4 4 5 5 4 4 5 4 5 4 5 4 5 4 6 4 . * * # 2 rcoccr register , , , 5 5 @ ' ) e % 4 @ / ) e % 4 @ 5 @ 1 a g 5 g 2 # % e e & / rcocr register ht45r37 rev. 1.20 28 february 25, 2011 the values in timer a and timer b is changed by writing to the high byte registers, tmrah and tmrbh, but writ - ing to the low byte registers tmral and tmrbl will keep the values in timer a and timer b unchanged. reading registers tmrah and tmrbh will also latch the tmral tmrbl values into the low byte buffer to avoid false timing problems. reading from registers tmral and tmrbl returns the contents of the low byte buffer only. therefore, the low byte of timer a and timer b cannot be read directly. tmrah and tmrbh must be read first to ensure that the low byte contents of timer a and timer b are latched into the buffer. the external resistor and capacitor, together with inter - nal inverters, form an oscillation circuit which is the clock source for timer b and therefore the input to registers tmrbl and tmrbh. the rcom0, rcom1 and rcom2 bits of rcoccr define the clock source of timer a. if the rcocon bit in the rcoccr register is set high, timer a and timer b will start counting until either timer a or timer b overflows. the relevant timer will then gen - erate an interrupt request flag which is the rcocf bit in the intc1 register. timer a and timer b will stop count - ing and will also reset the rcocon bit to zero at the same time. if the rcocon bit is set high, then the tmral/tmrah and tmrbl/tmrbh register cannot be read or written to. c/r to f converter analog switches the device contains only one internal c/r to f converter function, however it can be connected to any of the 16 external channels using its internal analog switch func- tion. this enables applications such as multi-channel or matrix touch switch applications to be implemented. the bits in the ascr0~ascr1 registers select which of the 16-channels is to be connected to the internal c/r to f converter. the bits in the ascr2 register selects what happens to the channel when the channel is inactive. when a channel is inactive it can be selected to be pulled low to ground or not using bits in the ascr2 reg - ister. as there are only 8-bits to control 16-channels the function is selected in channel pairs. there are configu - ration options which must first be selected to choose which pins are to be used as inputs to the c/r to f con - verter. if the configuration options have selected pa0~pa7 to be normal i/o pins, then the corresponding bit 0~bit7 bits in the ascr0 register will have no function and will be read as zero. similarly if the configuration options have selected pd0~pd7 to be normal i/o pins, then the corresponding bit 0~bit7 bits in the ascr1 register will have no function and will be read as zero. if the configuration options have selected pa0~pa7 to be normal i/o pins, then the corresponding bits in the ascr2 register, bit 0 ~ bit3, must be cleared to zero to disable the rc0/rc1, rc2/rc3, rc4/rc5 and rc6/rc7 pull-low resistors. similarly if the configuration options have selected pd0~pd7 to be normal i/o pins, then the corresponding bits in the ascr2 register, bit 4~bit7, must be cleared to zero to disable the rc8/rc9, rc10/rc11, rc12/rc13 or rc14/rc15 pull-low resistors. ' ; ; 5 ' ; ; 4 ' ; ; 4 2 ' ; ; 4 3 ' 5 ' 4 ' . 5 4 4 2 4 3 # 1 ! + / * ! + ' % 5 f 4 3 ' ; ; 5 f ' ; ; 4 3 5 f 4 3 % ( ' ) % 2 # ! 3 4 ( ' ) , + , ' 5 # ' 4 ' . analog switches and c/r to f oscillator ht45r37 rev. 1.20 29 february 25, 2011 , 5 5 4 @ 5 % 5 @ 5 # + ) 4 4 @ 4 % 5 @ 4 # + ) 6 4 @ 6 % 5 @ 6 # + ) ' 5 1 ' 4 1 ' 6 1 ascr0 register , 0 5 4 @ % 5 @ # + ) 9 4 @ 9 % 5 @ 9 # + ) 4 3 4 @ 4 3 % 5 @ 4 3 # + ) ' 1 ' 9 1 ' 4 3 1 ascr1 register , 5 5 # 4 4 @ 5 # 4 % 5 @ 5 # 4 e . # 0 4 @ . # 0 % 5 @ . # 0 e 2 # 3 4 @ 2 # 3 % 5 @ 2 # 3 e 7 # 6 4 @ 7 # 6 % 5 @ 7 # 6 e # 9 4 @ # 9 % 5 @ # 9 e 4 5 # 4 4 4 @ 4 5 # 4 4 % 5 @ 4 5 # 4 4 e 4 . # 4 0 4 @ 4 . # 4 0 % 5 @ 4 . # 4 0 e 4 2 # 4 3 4 @ 4 2 # 4 3 % 5 @ 4 2 # 4 3 e ' $ 1 5 ' $ 1 4 ' $ 1 . ' $ 1 0 ' $ 1 2 ' $ 1 3 ' $ 1 7 ' $ 1 6 ascr2 register ht45r37 rev. 1.20 30 february 25, 2011 programming example the following example shows the principles of how the c/r to f converter function is programmed: external rc oscillation converter mode example program - timer a overflow: clr rcoccr mov a, 00000010b ; enable external rc oscillation mode and set timer a overflow mov rcocr,a clr mfic0.1 ; clear external rc oscillation converter interrupt request flag clr mfic0.5 mov a, low (65536-1000) ; give timer a initial value mov tmral, a ; timer a count 1000 time and then overflow mov a, high (65536-1000) mov tmrah, a mov a, 00h ; give timer b initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b ; timer a clock source=f sys /4 and timer on mov rcoccr, a p10: clr wdt snz mfic0.5 ; polling external rc oscillation converter interrupt request flag jmp p10 clr mfic0.5 ; clear external rc oscillation converter interrupt request flag ; program continue ht45r37 rev. 1.20 31 february 25, 2011 pulse width modulator the device contains twos pulse width modulation, pwm, outputs. useful for such applications such as mo - tor speed control, the pwm function provides an output with a fixed frequency, but with a duty cycle that can be varied by setting particular values into the correspond - ing pwm register pair. channel pwm mode output pin register names 1 8+4 pd0 pwm0l~ pwm0h 2 8+4 pd1 pwm1l~ pwm1h pwm overview a register pair, located in the data memory is assigned to each pulse width modulator output and are known as the pwm registers. it is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. the pwm registers also contain the enable/dis - able control bit for the pwm outputs. to increase the pwm modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. note that it is only necessary to write the required modulation value into the corresponding pwm register as the subdivision of the waveform into its sub-modulation cycles is imple- mented automatically within the microcontroller hard- ware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation fre - quency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 12-bits wide, the overall pwm cycle frequency is f sys /4096. however, when in the 8+4 mode of operation, the pwm modulation frequency will be f sys /256. pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /256 f sys /4096 (pwm register value)/4096 8+4 pwm mode modulation each full pwm cycle, as it is 12-bits wide, has 4096 clock periods. however, in the 8+4 pwm mode, each pwm cy - cle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as i in the table. each one of these sixteen sub-cycles con - tains 256 clock cycles. in this mode, a modulation fre - quency increase of sixteen is achieved. the 12-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit4~bit11 is denoted here as the dc value. the second group which consists of bit0~bit3 is known as the ac value. in the 8+4 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~15) dc (duty cycle) modulation cycle i (i=0~15) i ac dc+1 256 i ac dc 256 8+4 mode modulation cycle values the accompanying diagram illustrates the waveforms associated with the 8+4 mode of pwm operation. it is important to note how the single pwm cycle is subdi- vided into 16 individual modulation cycles, numbered 0~15 and how the ac value is related to the pwm value. pwm output control the two outputs, pwm0 and pwm1, are shared with pins pd0 and pd1. to operate as a pwm output and not as an i/o pin, bit 0 of the relevant pwm low byte register bit must be set high. a zero must also be written to the corresponding bit in the pdc port control register, to en - sure that the pwm0 output pin is setup as an output. af - ter these two initial steps have been carried out, and of course after the required pwm 12-bit value has been written into the pwm register pair register, setting the corresponding bit in the pd data register high will enable the pwm data to appear on the pin. writing a zero to the bit will disable the pwm output function and force the output low. in this way, the port d data output register bits, can also be used as an on/off control for the pwm function. note that if the enable bit in the pwm register is set high to enable the pwm function, but if the corre - sponding bit in the pdc control register is high to config - ure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. ht45r37 rev. 1.20 32 february 25, 2011 5 + 6 5 # e e 4 @ 5 @ # 1 a g 5 g ' & 5 f 0 ( & 2 f 4 4 ! 1 5 0 4. 6 5 4 4 94 5 6 7 3 2 5 $ f 4 $ $ % / 5 c f 4 c c / pwm register pairs e ? # . b d j 4 7 5 5 b d j 4 7 5 4 b d j 4 7 5 . b d j 4 7 4 3 @ 2 5 9 7 # e ? 4 5 5 # . 3 7 4 5 4 # . 3 7 4 5 4 # . 3 7 4 5 4 # . 3 7 5 @ . 3 7 # e ? 4 . 4 3 5 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 4 # . 3 7 4 5 5 # . 3 7 4 5 4 # . 3 7 4 5 4 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 5 # . 3 7 4 5 4 # . 3 7 4 5 4 # . 3 7 4 5 4 # . 3 7 8+4 pwm mode pwm programming example the following sample program shows how the pwm output is setup and controlled. mov a,64h ; setup pwm0 value to 1600 decimal which is 640h mov pwm0h,a ; setup pwm0h register value clr pwm0l ; setup pwm0l register value clr pdc.0 ; setup pin pd0 as an output set pwm0en ; set the pwm0 enable bit set pd.0 ; enable the pwm0 output :: :: clr pd.0 ; pwm0 output disabled pd0 will remain low ht45r37 rev. 1.20 33 february 25, 2011 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller , the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains an 6-channel analog to digital con - verter which can directly interface to external analog sig - nals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit dig - ital value. input channels conversion bits input pins 6 12 pb0~pb5 the accompanying block diagram shows the overall in - ternal structure of the a/d converter, together with its as - sociated registers. a/d converter data registers adrl, adrh the device, which has an internal 12-bit a/d converter, requires two data registers, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digit- ised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte regis- ter utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers a/d converter control registers adcr, acsr to control the function and operation of the a/d con - verter, two control registers known as adcr and acsr are provided. these 8-bit registers define functions such as the selection of which analog channel is con - nected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of con - version status. the acs2~acs0 bits in the adcr register define the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 6 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the internal a/d converter. the adcr control register also contains the pcr2~pcr0 bits which determine which pins on port b are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. note that if the pcr2~pcr0 bits are all set to zero, then all the port b pins will be setup as normal i/os and the internal a/d converter circuitry will be powered off to reduce the power consumption. the start bit in the register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital * ( ) 1 ' ' ( / 5 # ' 1 5 / 4 # ' 1 4 / 3 # ' 1 3 ' # ( e & ' ( $ ' ( c ' # ( ( 5 f . ' ( 5 f ' ( . ' ! / ' ( ' & ' # ( - ' & ( ( ' # ( ) % ' ( 1 / / ' # ( ! e ? a/d converter structure ht45r37 rev. 1.20 34 february 25, 2011 conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is com- plete. this bit will be automatically cleared to zero by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detect - ing the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs2, adcs1 and adcs0 bits in the acsr register. controlling the on/off function of the a/d converter cir - cuitry is implemented using the adonb bit in the acsr register and the value of the pcr bits in the adcr reg - ister. both the adonb bit must cleared to zero and the value of the pcr bits must have a non-zero value for the a/d converter to be enabled. pcr adonb a/d 0 x off >0 0 on > 0 1 off although the a/d clock source is determined by the sys - tem clock f sys , and by bits adcs2, adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad ,is0.5 s, care must be taken for system clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs2, adcs1 and adcs0 bits should not be set to 000 . doing so will give a/d clock periods that are less than the mini - mum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for exam - ples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum a/d clock period. 6 5 ' . 4 5 ' . ' 4 ' 5 ! / , ' # ( / ' # ( e ! e ' # ( ) e 4 @ ' # ( ) % 5 @ ' # ( ) ' # ( ) 5 4 5 @ 5 4 @ ' # ( ) ! / g 4 g ' . 5 5 5 5 4 4 4 4 ' 4 5 5 4 4 5 5 4 4 ' 5 5 4 5 4 5 4 5 4 ' 1 5 ' 1 4 ' 1 . ' 1 0 ' 1 2 ' 1 3 ' 1 3 ' 1 3 . 5 5 5 5 4 4 4 4 4 5 5 4 4 5 5 4 4 5 5 4 5 4 5 4 5 4 / ' # ( e e / 5 ' 1 5 / 5 f / 4 ' 1 5 f ' 1 4 / 5 f / . ' 1 5 f ' 1 . / 5 f / 0 ' 1 5 f ' 1 0 / 5 f / 2 ' 1 5 f ' 1 2 / 5 f / 3 ' 1 5 f ' 1 3 / 5 f / 6 ' 1 5 f ' 1 3 a/d converter control register adcr ht45r37 rev. 1.20 35 february 25, 2011 ' # ( ) * 1 a g 5 g ' # ( # e e 4 @ 5 @ + , 5 ' ( 4 ' ( 5 ' ( 4 5 5 4 4 5 5 4 4 ' ( 5 5 4 5 4 5 4 5 4 @ * # . @ * # @ * # 0 . @ e @ * @ * # 2 @ * # 4 7 @ e 6 ! ' ( 1 / ' ( . ' ( . 5 5 5 5 4 4 4 4 a/d converter control register acsr f sys a/d clock period (t ad ) adcs2, adcs1, adcs0=000 (f sys /2) adcs2, adcs1, adcs0=001 (f sys /8) adcs2, adcs1, adcs0=010 (f sys /32) adcs2, adcs1, adcs0=011 1mhz 2s8 s3 2 s undefined 2mhz 1s4 s1 6 s undefined 4mhz 500ns* 2s8 s undefined 8mhz 250ns* 1s4 s undefined 12mhz 167ns* 667ns* 2.67s undefined a/d clock period examples a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port b. bits pcr2~pcr0 in the adcr regis- ter, determine whether the input pins are setup as nor- mal port b input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high re - sistors, which are setup through register programming, apply to the input pins only when they are used as nor - mal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to first setup the a/d pin as an input in the pbc port control register to enable the a/d input as when the pcr2~pcr0 bits enable an a/d input, the sta - tus of the port control register will be overridden. the a/d converter has its own power supply pins avdd and avss pin. the analog input values must not be allowed to exceed the value of avdd. initialising the a/d converter the internal a/d converter must be initialised in a special way. each time the port b a/d channel selection bits are modified by the program, the a/d converter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb flag may have an undefined value, which may produce a false end of conversion signal. to initialise the a/d converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the start bit in the adcr register must first be set high and then im- mediately cleared to zero. this will ensure that the eocb flag is correctly set to a high condition. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process. step 1 select the required a/d conversion clock by correctly programming bits adcs2, adcs1 and adcs0 in the register. step 2 enable the a/d by clearing the in the acsr register to zero. step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the reg - ister. step 4 select which pins on port b are to be used as a/d in - puts and configure them as a/d input pins by correctly programming the pcr2~pcr0 bits in the adcr reg - ister. note that this step can be combined with step 2 into a single adcr register programming operation. ht45r37 rev. 1.20 36 february 25, 2011 step 5 if the interrupts are to be used, the interrupt control reg - isters must be correctly configured to ensure the a/d converter interrupt function is active. the master inter - rupt control bit, emi, in the intc0 interrupt control reg- ister must be set to 1 , the multi-function interrupt enable bit, emfi1, in the intc1 register and the a/d converter interrupt bit, eadi, in the mfic1 register must also be set to 1 . step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis- ter from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0. step 7 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the in - terrupts are enabled and the stack is not full, the pro - gram can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the vari - ous stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter func - tion is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period. programming considerations when programming, special attention must be given to the a/d channel selection bits in the register. if these bits are all cleared to zero no external pins will be se- lected for use as a/d input pins allowing the pins to be used as normal i/o pins. when this happens the power supplied to the internal a/d circuitry will be reduced re- sulting in a reduction of supply current. this ability to re- duce power by turning off the internal a/d function by clearing the a/d channel selection bits may be an impor - tant consideration in battery powered applications. the adonb bit in the acsr register can also be used to power down the a/d function. another important programming consideration is that when the a/d channel selection bits change value, the a/d converter must be re-initialised. this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not re - quired to be re-initialised. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. ' ( ' # ( ) 5 5 5 / " " " / 4 5 5 / 5 4 5 / ' ! / . f 5 ' . f ' 5 % ! e ' # ( ) 4 @ ( e e . @ ' # ( * e a e ? # . a e ? # 2 a e ? # a e ? # 4 7 e ? # 0 . ' ( j 2 ' ( ' ( j ' ( > k ' ( l j e ' ( 1 @ e ' # ( ) ' # ( ) ' # ( ' ( 5 5 5 / e ' # ( ) ' # ( ) 4 5 4 / 5 5 4 / e ' # ( ) ' # ( ) ! e ' # ( ) ' # ( ' ( 5 5 5 / " " " / ' ( 1 ' ( 1 / e e e e 1 . ' ( ' # ( ) a/d conversion timing ht45r37 rev. 1.20 37 february 25, 2011 example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the ; following start ; signal (0-1-0) must be issued ; instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and turn on adonb bit mov a,00100000b ; setup adcr register to configure port pb0~pb3 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d : ; as the port b channel bits have changed the ; following start signal(0-1-0) must be issued ; : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emfi1 ; enable multi-function 1 interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defined memory a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit__isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory clr adf ; clear adc interrupt flag reti ht45r37 rev. 1.20 38 february 25, 2011 a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the av dd voltage, this gives a single bit analog input value of av dd /4096. the diagram show the ideal transfer func - tion between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb off- set is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the av dd level. serial interface function the device contains a serial interface function, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of commu - nication with external peripheral hardware. having rela - tively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim in - terface function must first be selected using a configura - tion option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using a bit in an internal register. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require - ments when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the mcu can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, here, as only a single select pin, scs , is provided only one slave device can be connected to the spi bus. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the se - rial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the sim enable configura - tion option and setting the correct bits in the simctl0/simctl2 register. after the spi configuration option has been configured it can also be additionally disabled or enabled using the simen bit in the simctl0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilised. the spi function in this device offers the following fea - tures: full duplex synchronous data transfer both master and slave modes + + ! c < = ' # ( ) + + + c + + ( c 5 0 c 5 . c 5 4 c 5 ; 3 $ / 5 4 . 0 2 5 9 0 2 5 9 2 2 5 9 3 2 5 9 7 ' & 4 ; 3 $ / ' & ( ( 2 5 9 7 ideal a/d transfer function + ' ) ' 6 8 ( ( 8 ( ( spi master/slave connection ht45r37 rev. 1.20 39 february 25, 2011 ( / ( ( ( " # " e / e + + ! # ( $ + * ! # * e ? e / # ! ) 8 e ! 1 ! # ( 8 ! 1 8 $ spi block diagram lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen, simen and scs . in the table i, z represents an input floating condition. there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. another two sim configuration options determine if the csen and wcol bits are to be used. configuration option function sim function sim interface enable/disable spi csen bit enable/disable spi wcol bit enable/disable spi interface configuration options spi registers there are three internal registers which control the over - all operation of the spi interface. these are the simdr data register and two control registers simctl0 and simctl2. note that the simctl1 register is only used by the i 2 c interface. pin master/salve simen=0 master simen=1 slave simen=1 csen=0 csen=1 csen=0 csen=1 scs =0 csen=1 scs =1 scs zzlzi , zi , z s d ozooooz sdi z i, z i, z i, z i, z z sck z h: ckpol=0 l: ckpol=1 h: ckpol=0 l: ckpol=1 i, z i, z z note: z floating, h output high, l output low, i input, o output level, i,z input floating (no pull-high) spi interface pin status ht45r37 rev. 1.20 40 february 25, 2011 + , $ 1 a m 5 g # . # e 4 @ 5 @ * % # . # ) * . 4 5 5 ! 1 a e ? # 2 a e ? # 4 7 a e ? # 7 2 a e / a # ! ) 5 # . ) . 1 5 5 5 5 4 4 4 4 5 5 4 4 5 5 4 4 6 4 5 . 5 4 5 4 5 4 5 4 8 ! 1 8 4 8 5 spi/i 2 c control register simctl0 + , $ 6 # ) e 4 @ e 5 @ e 4 @ 5 @ 4 @ 5 @ e ( e 4 @ / 5 @ $ / * ! 4 @ " 5 @ " * 4 @ " 5 @ " 1 a g 5 g 5 $ + ! 1 $ 8 ! - 8 $ spi control register simctl2 + , $ 0 6 ) * % e 4 @ * % 5 @ * % 1 a g 5 g # % , e 4 @ , 5 @ , % * % e 4 @ m * % 5 @ * % # ) 4 @ 5 @ ) . e 4 @ 5 @ e 4 @ 5 @ ( e e 4 @ e 5 @ e 5 c h h ' 8 h ' 8 c / / c ' ' c + i 2 c control register simctl1 ht45r37 rev. 1.20 41 february 25, 2011 the simdr register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the microcontroller writes data to the spi bus, the actual data to be transmitted must be placed in the simdr reg - ister. after the data is received from the spi bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the spi bus must be made via the simdr register. bit76543210 label sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w there are also two control registers for the spi inter - face, simctl0 and simctl2. note that the simctl2 register also has the name simar which is used by the i 2 c function. the simctl1 register is not used by the spi function, only by the i 2 c function. register simctl0 is used to control the enable/disable function and to set the data transmission clock frequency. al - though not connected with the spi function, the simctl0 register is also used to control the peripheral clock prescaler. register simctl2 is used for other control functions such as lsb/msb selection, write colli - sion flag etc. the simidle bit in the clkmod register is used to select if the sim continues running when the de- vice is in the idle mode. setting the bit high allows the sim to maintain operation when the device is in the idle mode. clearing the bit to zero disables any sim opera- tions when in the idle mode. the following gives further explanation of each simctl1 register bit: simen the bit is the overall on/off control for the spi inter - face. when the simen bit is cleared to zero to disable the spi interface, the sdi, sdo, sck and scs lines will be in a floating condition and the spi operating current will be reduced to a minimum value. when the bit is high the spi interface is enabled. the sim config - uration option must have first enabled the sim inter - face for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condi - tion and should therefore be first initialised by the ap - plication program. sim0~sim2 these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selec - tion and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the timer/event counter. if the spi slave mode is selected then the clock will be supplied by an external master device. sim0 sim1 sim2 spi master/slave clock control and i2c enable 0 0 0 spi master, f sys /4 0 0 1 spi master, f sys /16 0 1 0 spi master, f sys /64 0 1 1 spi master, f sub 100 spi master timer/event counter 0 output/2 1 0 1 spi slave 110i 2 c mode 1 1 0 not used ht45r37 rev. 1.20 42 february 25, 2011 8 < 8 $ j 4 = 8 < 8 $ j 5 = ( ( ( ( 6 # ( 5 ( 7 # ( 4 ( 3 # ( . ( 2 # ( 0 ( 0 # ( 2 ( . # ( 3 ( 4 # ( 7 ( 5 # ( 6 ( < ( e 8 = spi slave mode timing (ckeg=0) 8 < 8 $ j 4 a 8 ! - j 5 = ! 1 a ! 1 j 4 ! 1 j 4 a ! 1 j 5 < ! " c = 8 < 8 $ j 5 a 8 ! - j 5 = 8 < 8 $ j 4 a 8 ! - j 4 = 8 < 8 $ j 5 a 8 ! - j 4 = ( < 8 ! - j 5 = ( < 8 ! - j 4 = ( ( ( 6 # ( 5 ( 7 # ( 4 ( 3 # ( . ( 2 # ( 0 ( 0 # ( 2 ( . # ( 3 ( 4 # ( 7 ( 5 # ( 6 ( 6 # ( 5 ( 7 # ( 4 ( 3 # ( . ( 2 # ( 0 ( 0 # ( 2 ( . # ( 3 ( 4 # ( 7 ( 5 # ( 6 ( spi master mode timing 8 < 8 $ j 4 = 8 < 8 $ j 5 = ( ( ( ( 6 # ( 5 ( 7 # ( 4 ( 3 # ( . ( 2 # ( 0 ( 0 # ( 2 ( . # ( 3 ( 4 # ( 7 ( 5 # ( 6 ( < ( % l ( j e e j 4 = 1 @ + ) a e ! 1 j 4 ! 1 j 5 a % ) ; spi slave mode timing (ckeg=1) ht45r37 rev. 1.20 43 february 25, 2011 ! 1 j 4 ( ( $ j 4 n $ ? n < + j 4 n = 1 ? ( e ( + e + n 1 ? ! 1 ( ) ) ' ' e e ! 1 $ b . @ 5 d j 5 5 5 a 5 5 4 a 5 4 5 a 5 4 4 4 5 5 b . @ 5 d j 4 5 4 1 spi transfer control flowchart ht45r37 rev. 1.20 44 february 25, 2011 spi control register simctl2 the simctl2 register is also used by the i 2 c interface but has the name simar . trf the trf bit is the transmit/receive complete flag and is set high automatically when an spi data transmis - sion is completed, but must be cleared by the applica - tion program. it can be used to generate an interrupt. wcol the wcol bit is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simdr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via configu - ration option. csen the csen bit is used as an on/off control for the scs pin. if this bit is low then the scs pin will be disabled and placed into a floating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or en - abled via configuration option. mls this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. ckeg and ckpol these two bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data trans- fer is executed otherwise an erroneous clock edge may be generated. the ckpol bit determines the base condition of the clock line, if the bit is high then the sck line will be low when the clock is inactive. when the ckpol bit is low then the sck line will be high when the clock is inactive. the ckeg bit deter - mines active clock edge type which depends upon the condition of ckpol . ckpol ckeg sck clock signal 00 high base level active rising edge 01 high base level active falling edge 10 low base level active falling edge 11 low base level active rising edge spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simdr register, transmission/reception will begin si - multaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi pin will be shifted into the simdr regis - ter. the master should output an scs signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled be - fore/after an scs signal is received. the spi will continue to function even after a halt in - struction has been executed. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data trans - fer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many de- vices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are con- nected to these outputs. note that no chip select line ex- ists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master de - vice that has overall control of the bus. for these de - vices, which only operates in slave mode, there are two ' e ) # e ' * % e ) e ' * % e ) e ht45r37 rev. 1.20 45 february 25, 2011 methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. a configuration option exists to allow a clock other than the system clock to drive the i 2 c inter - face. another configuration option determines the debounce time of the i 2 c interface. this uses the inter- nal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. sim function sim function sim interface enable or disable i 2 c debounce no debounce, 1 system clock; 2 system clocks i 2 c interface configuration options i 2 c registers there are three control registers associated with the i 2 c bus, simctl0, simctl1 and simar and one data reg - ister, simdr . the simdr register, which is shown in the above spi section, is used to store the data being trans - mitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simdr register. after the data is received from the i 2 c bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the i 2 c bus must be made via the simdr register. note that the simar register also has the name simctl2 which is used by the spi function. bits simidle , simen and bits sim0~sim2 in register simctl0 are used by the i 2 c interface. the simctl0 register is shown in the above spi section. simidle the simidle bit is used to select if the i 2 c interface continues running when the device is in the idle mode. setting the bit high allows the i 2 c interface to maintain operation when the device is in the idle mode. clearing the bit to zero disables any i 2 c opera - tions when in the idle mode. this spi/i 2 c idle mode control bit is located at clkmod register bit4. simen the simen bit is the overall on/off control for the i 2 c interface. when the simen bit is cleared to zero to dis- able the i 2 c interface, the sda and scl lines will be in a floating condition and the i 2 c operating current will be reduced to a minimum value. when the bit is high the i 2 c interface is enabled. the sim configuration op- tion must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the i 2 c con - trol registers will be in an unknown condition and should therefore be first initialised by the application program sim0~sim2 these bits setup the overall operating mode of the sim function. to select the i 2 c function, bits sim2~ sim0 should be set to the value 110. rxak the rxak flag is the receive acknowledge flag. when the rxak bit has been reset to zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxak bit to determine if the receiver wishes to receive the next byte. the transmitter will therefore continue sending out data until the rxak bit is set high. when this occurs, the device will release the sda line to al - low the master to send a stop signal to release the bus. . ( < ( = ) ' < ' = e ( h ' c ' ' / . ( $ / ( / # ) ( ( ( / ' ! # ( ' * % # % ) / c / / / c h / $ ( ' c + / i 2 c block diagram ht45r37 rev. 1.20 46 february 25, 2011 srw the srw bit is the slave read/write bit. this bit de - termines whether the master device wishes to trans - mit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haas bit is set high, the device will check the srw bit to determine whether it should be in transmit mode or receive mode. if the srw bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the srw bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. txak the txak flag is the transmit acknowledge flag. after the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. htx the htx flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. hbb the hbb flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. hass the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the ad - dresses match then this bit will be high, if there is no match then the flag will be low. hcf the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an in - terrupt will be generated. i 2 c control register simar the simar register is also used by the spi interface but has the name simctl2. the simar register is the location where the 7-bit slave address of the microcontroller is stored. bits 1~7 of the simar register define the microcontroller slave ad - dress. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simar register, the microcontroller slave device will be selected. note that the simar register is the same register as simctl2 which is used by the spi interface. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmis - sion, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de- vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simctl1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service rou- tine, the microcontroller slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the microcontroller to de - termine whether to go into transmit or receive mode. be - fore any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. + 6 e . ) ) 5 ' 3 ' 2 ' 7 ' 5 ' 0 ' . ' 4 i 2 c slave address register simar ) ' ' ! b . @ 5 d j 4 4 5 ! ! 1 . / j n ! ( ! ! ! + 5 e - $ ! + % . / - i 2 c bus initialisation flow chart ht45r37 rev. 1.20 47 february 25, 2011 c ' ' j 4 n c h j 4 n j 4 n ? 1 ? 1 h ' 8 j 4 n ? 1 1 e ( ! ? ( e ( ! ! ( ! c h ( ( + ( $ c h $ h ' 8 ! ! $ c h $ h ' 8 i 2 c bus isr flow chart ( 4 5 4 5 5 4 55 4 5 5 4 5 4 5 4 4 j < 4 = ' j ) ' < 6 = j < 4 = j ) ) * % < 4 = ( j ( < = ' j ' 8 < h ' 8 e a h ' 8 e ) 4 = j < 4 = $ ( ' ' 8 ' 8 $ ( ' ) ' ' ( ' ( ' ' ( ' ( ' i 2 c communication timing diagram ht45r37 rev. 1.20 48 february 25, 2011 step 2 set the simen bit in the simctl0 register to 1 to en - able the i 2 c bus. step 3 set the esim and emfi0 bits of the interrupt control register to enable the i 2 c bus interrupt. start signal the start signal can only be generated by the mas - ter device connected to the i 2 c bus and not by the microcontroller , which is only a slave device. this start signal will be detected by all devices con - nected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to deter - mine which slave device the master wishes to com - municate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, de- fines the read/write status and will be saved to the srw bit of the simctl1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the in - terrupt source has come from a matching slave ad - dress or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr regis - ter to release the scl line. srw bit the srw bit in the simctl1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srw bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the microcontroller slave device must check the srw bit to determine if it is to be a transmitter or a receiver. if the srw bit is high, the microcontroller slave device should be setup to be a transmitter so the htx bit in the simctl1 register should be set to 1 if the srw bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simctl1 register should be set to 0. data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge sig - nal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sda line and the master will send out a stop signal to re - lease control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simdr regis- ter. if setup as a receiver, the microcontroller slave de- vice must read the transmitted data from the simdr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxak bit in the simctl1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. $ ( ' ( ( % data timing diagram ht45r37 rev. 1.20 49 february 25, 2011 buzzer operating in a similar way to the programmable fre - quency divider, the buzzer function provides a means of producing a variable frequency output, suitable for ap - plications such as piezo-buzzer driving or other external circuits that require a precise frequency generator. buzzer operation the bz and bz pins form a complementary pair, and are pin-shared with i/o pins, pa0 and pa1. a configuration option is used to select from one of three buzzer options. the first option is for both pins pa0 and pa1 to be used as normal i/os, the second option is for both pins to be configured as bz and bz buzzer pins, the third option selects only the pa0 pin to be used as a bz buzzer pin with the pa1 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which to - gether generate a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, , which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from f s /2 2 to f s /2 9 . the clock source that generates f s , which in turn controls the buzzer fre - quency, can originate from three different sources, the 32768hz oscillator, the 32k_int oscillator or the sys - tem oscillator/4, the choice of which is determined by the f s clock source configuration option. note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock f s and the internal division ratio. there are no internal registers associated with the buzzer frequency. if the configuration options have selected both pins pa0 and pa1 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by set - ting bits pac0 and pac1 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low, both pins pa0 and pa1 will remain low. in this way the single bit pa0 of the pa register can be used as an on/off control for both the bz and bz buzzer pin outputs. note that the pa1 data bit in the pa register has no control over the bz buzzer pin pa1. e e e ? # 2 0 . 6 7 c o 0 . 8 p 1 e ( ) . . f . 9 e / : / : buzzer function pa0/pa1 pin function control pac register pac0 pac register pac1 pa data register pa0 pa data register pa1 output function 001x pa0=bz pa1=bz 000x pa0=0 pa1=0 011x pa0=bz pa1=input line 010x pa0=0 pa1=input line 10xd pa0=input line pa1=d 11xx pa0=input line pa0=input line x stands for don t care d stands for data 0 or 1 ht45r37 rev. 1.20 50 february 25, 2011 if configuration options have selected that only the pa0 pin is to function as a bz buzzer pin, then the pa1 pin can be used as a normal i/o pin. for the pa0 pin to func - tion as a bz buzzer pin, pa0 must be setup as an output by setting bit pac0 of the pac port control register to zero. the pa0 data bit in the pa data register must also be set high to enable the buzzer output, if set low pin pa0 will remain low. in this way the pa0 bit can be used as an on/off control for the bz buzzer pin pa0. if the pac0 bit of the pac port control register is set high, then pin pa0 can still be used as an input even though the configuration option has configured it as a bz buzzer output. note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the con - figuration option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the ac - tual function of the pin can be changed dynamically by the application program by programming the appropri - ate port control register bit. * ' 5 ( / : ' 5 / : ' 4 ' 4 ( buzzer output pin control note: the above drawing shows the situation where both pins pa0 and pa1 are selected by configuration option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as out- put. the data setup on pin pa1 has no effect on the buzzer outputs. ht45r37 rev. 1.20 51 february 25, 2011 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or an a/d converter re - quires microcontroller attention, their corresponding in - terrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are controlled by the action of the ex - ternal int0, int1 and pint pins, while the internal in - terrupts are controlled by functions such as the timer/event counter overflows, the time base inter - rupt, the rtc interrupt, the spi/i 2 c interrupt, c/r to f converter interrupt and the a/d converter interrupt etc. interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the intc0, intc1, mfic0, and mfic1 registers, which are located in the data memory. by controlling the appropriate en - able bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller . the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer/event counter overflow, time base, rtc over- flow, spi/i 2 c data transfer complete, c/r to f converter interrupt, an end of a/d conversion or the external inter- rupt line being triggered are some of the events which will generate an interrupt request by setting their corre- sponding request flag. when this happens and if their appropriate interrupt enable bit is set, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new ad - dress which will be the value of the corresponding inter - rupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h multi function 0 interrupt 5 14h multi function 1 interrupt 6 18h the spi/i 2 c interrupt, c/r to f converter interrupt share the same vector which is multi function 0 interrupt vec- tor at location 14h. the a/d converter interrupt, real time clock interrupt, time base interrupt and external peripheral interrupt share the same vector which is the multi function 1 interrupt vector at location 18h. each interrupt has its own interrupt flag but share the global mf0f or mf1f multi function interrupt flag. the mf0f and mf1f flags will be cleared by hardware once the multi-function interrupt is serviced, however the individ - ual interrupts that have triggered the multi-function inter - rupt need to be cleared by the application program external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bits, eei0 and eei1, must first be set. additionally the correct interrupt edge type must be selected using the intedge register to enable the external interrupt function and to choose the trigger edge type. an actual external interrupt will take place when the external interrupt request flag, eif0 or eif1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the int0 or int1 pin. the external interrupt pins are pin-shared with the i/o pins pa6 and pa7 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the intc0 register has been set. ht45r37 rev. 1.20 52 february 25, 2011 , 4 @ 5 @ ! " 5 4 @ 5 @ ! " 4 4 @ 5 @ # ! ) 5 4 @ 5 @ ! " 5 , e 4 @ ) 5 @ ) ! " 4 , e 4 @ ) 5 @ ) # ! ) 5 , e 4 @ ) 5 @ ) 1 a g 5 g 6 5 ! ! 4 ! ! 5 ! ! + 5! + 4 ! 5 5 + interrupt control register intc0 , 0 # ! ) 4 4 @ 5 @ + 5 4 @ 5 @ e 4 4 @ 5 @ 1 a g 5 g # ! ) 4 , e 4 @ ) 5 @ ) + 5 , e 4 @ ) 5 @ ) e 4 , e 4 @ ) 5 @ ) 1 a g 5 g 6 5 ! + 4 ! + 5 ! 4 4 + + 5 + + 4 + interrupt control register intc1 ht45r37 rev. 1.20 53 february 25, 2011 + , # . 4 @ 5 @ # + ) 4 @ 5 @ 1 a g 5 g # . , e 4 @ ) 5 @ ) # + ) , e 4 @ ) 5 @ ) 1 a g 5 g 5 ! ! + 6 + interrupt control register mfic0 + , 0 ' # ( ) 4 @ 5 @ * 4 @ 5 @ / 4 @ 5 @ ! " 4 @ 5 @ ' # ( ) , e 4 @ ) 5 @ ) * , e 4 @ ) 5 @ ) / , e 4 @ ) 5 @ ) ! " , e 4 @ ) 5 @ ) 6 5 ! / ! ! ' ( ' ( + + / + ! ! + interrupt control register mfic1 ht45r37 rev. 1.20 54 february 25, 2011 ' " e ' ( + a / + a + a ! + a + + e % ' ( ! c ! " , + ! + 4 ! ! 5 # ! ) 5 , + 5 + ! ! 4 ! 5 # ! ) 4 , + 4 + ! 4 + 5 , + + 5 + ! + 5 ! " , + ! + 5 e 4 , + + 4 + ! + 4 ! $ % / , + / + ! ' ( * , + + ! ' # ( ) , + ' ( + ! / ! # . , + + ! # + ) , + + ! ! " , + ! + interrupt structure the pin must also be setup as an input by setting the corresponding pac.6 and pac.7 bits in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h or 08h, will take place. when the interrupt is serviced, the external interrupt request flags, eif0 or eif1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. the intedge register is used to select the type of active edge that will trigger the external interrupt. a choice of ei - ther rising and falling edge types can be chosen along with an option to allow both edge types to trigger an exter - nal interrupt. note that the intedge register can also be used to disable the external interrupt function. the external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external inter - rupts due to adverse noise or spikes on the external in - terrupt input signal. as this internal filter circuit will consume a limited amount of power, a configuration op - tion is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. care must be taken when using the filter on/off configuration option as it will be applied not only to both the external interrupt pins but also to the timer/event counter exter - nal input pins. individual external interrupt or timer/event counter pins cannot be selected to have a filter on/off function. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within multi-function interrupt 1. for an external peripheral interrupt to occur, the global interrupt enable bit, emi, external peripheral interrupt enable bit, epi, and multi-function interrupt 1 enable bit, ht45r37 rev. 1.20 55 february 25, 2011 emf1i, must first be set. an actual external peripheral interrupt will take place when the external interrupt re - quest flag, pef, is set, a situation that will occur when a negative transition, appears on the pint pin. when the interrupt is enabled, the stack is not full and a negative transition type appears on the external peripheral inter - rupt pin, a subroutine call to the multi-function interrupt 1 vector at location18h, will take place. when the external peripheral interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf1f interrupt request flag will be reset. as the pef flag will not be automatically reset, it has to be cleared by the application program. the pin must also be setup as an input by setting high the corresponding pdc.6 bit in the port control register. note that any pull-high resistor software configuration on this pin will remain valid even if the pin is used as an external interrupt input. timer/event counter interrupt for a timer/event counter 0 or timer/event counter 1 interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i must first be set. an actual timer/event counter in - terrupt will take place when the timer/event counter re - quest flag, t0f or t1f is set, a situation that will occur when the timer/event counter overflows. when the in - terrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 0ch or 10c, will take place. when the interrupt is serviced, the timer interrupt re - quest flag, t0f or t1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. a/d interrupt the a/d interrupt is contained within the multi-function interrupt 1. for an a/d interrupt to be generated, the global interrupt enable bit, emi, a/d interrupt enable bit, eadi, and multi-function interrupt 1 enable bit, emf1i, must first be set. an actual a/d interrupt will take place when the a/d interrupt request flag, adf, is set, a situation that will oc - cur when the a/d conversion process has finished. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the multi-function interrupt 1 vector at location18h, will take place. when the a/d interrupt is serviced, the emi bit will be cleared to disable other in - terrupts, however only the mf1f interrupt request flag will be reset. as the adf flag will not be automatically re - set, it has to be cleared by the application program. multi-function interrupts additional interrupts known as the multi-function inter- rupts are provided. unlike the other interrupts, these in- terrupts have no independent source, but rather are formed from other existing interrupt sources, namely the a/d converter interrupt, time base interrupt, real time clock interrupt, external peripheral interrupt, sim inter- face interrupt and the c/r to f interrupt. for a multi-function interrupt to occur, the global interrupt enable bit, emi, and the multi-function interrupt enable bit, emf0i or emf1i, must first be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mf0f, or mf1f is set. this will occur when either a time base overflow, a real time clock overflow, an a/d conversion completion, an external peripheral interrupt, c/r to f converter coun - ters, timer a or timer b overflow or sim data transfer or i2c address match occurs. when the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the multi-function interrupts occurs, a subroutine call to one of the multi-function interrupt vector at location 014h or 018h will take place. when the inter - rupt is serviced, the multi-function request flag, mf0f or mf1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. how - ever, it must be noted that the request flags from the origi - nal source of the multi-function interrupt, namely the time-base interrupt, real time clock interrupt, a/d con - verter interrupt, external peripheral interrupt, sim inter - face or c/r to f converter interrupt will not be 3 7 3 1 5 ! 1 5 4 1 5 5 1 4 ! ( 1 4 4 1 4 5 1 a g 5 g 5 1 4 5 1 5 4 1 5 5 6 1 4 4 5 5 4 4 5 4 5 4 e 5 5 4 4 5 4 5 4 e interrupt active edge register intedge ht45r37 rev. 1.20 56 february 25, 2011 automatically reset and must be manually reset by the application program. spi/i 2 c interface interrupt the spi/i 2 c interface interrupt is contained within the multi-function interrupt 0. for an /i 2 c interrupt to occur, the global interrupt enable bit, emi, the corresponding interrupt enable bit, esim and multi-function interrupt 0 enable bit, emf0i, must be first set. an actual spi/i 2 c interrupt will take place when the spi/i 2 c reset function interface request flag, simf, is set, a situation that will occur when a byte of data has been transmitted or received by the spi/i 2 c interface or when an i 2 c address match occurs. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spi/i 2 c interface or an i 2 c address match occurs, a subroutine call to the multi-function interrupt 0 vector at location 14h, will take place. when the interrupt is serviced, the multi-function interrupt 0 request flag, mf0f, will be automatically re - set and the emi bit will be automatically cleared to dis - able other interrupts. as the simf flag will not be automatically reset it has to be cleared by the applica - tion program. c/r to f converter interrupt the c/r to converter interrupt is contained within the multi-function interrupt 0. for a c/r to f converter interrupt to be generated, the global interrupt enable bit, emi, the corresponding inter- rupt enable bit, ercoci and multi-function interrupt 0 enable bit, emf0i, must be first set. an actual c/r to f converter interrupt will take place when the c/r to f converter interrupt request flag, rcocf, is set, a situa- tion that will occur when one of the c/r to f converter counters, timer a or timer b, overflows. when the inter - rupt is enabled, the stack is not full and a c/r to f con - verter counter overflow occurs, a subroutine call to the multi-function interrupt 0 vector at location 14h, will take place. when the interrupt is serviced, the multi-function interrupt 0 request flag, mf0f, will be automatically re - set and the emi bit will be automatically cleared to dis - able other interrupts. as the rcocf flag will not be automatically reset it has to be cleared by the applica - tion program. real time clock interrupt the real time clock interrupt is contained within the multi-function interrupt 1. for a real time clock interrupt to be generated, the global interrupt enable bit, emi , real time clock inter - rupt enable bit, erti, and multi-function interrupt 1 en - able bit, emf1i, must first be set. an actual real time clock interrupt will take place when the real time clock request flag, rtf, is set, a situation that will occur when the real time clock overflows. when the interrupt is en - abled, the stack is not full and the real time clock over - flows, a subroutine call to the multi-function interrupt 1 vector at location18h, will take place. when the real time clock interrupt is serviced, the emi bit will be cleared to disable other interrupts, however only the mf1f interrupt request flag will be reset. as the rtf flag will not be automatically reset, it has to be cleared by the application program. similar in operation to the time base interrupt, the pur - pose of the rtc interrupt is also to provide an interrupt signal at fixed time periods. the rtc interrupt clock source originates from the internal clock source f s . this f s input clock first passes through a divider, the division ratio of which is selected by programming the appropri - ate bits in the rtcc register to obtain longer rtc inter - rupt periods whose value ranges from 2 8 /f s ~2 15 /f s . the clock source that generates f s , which in turn controls the rtc interrupt period, can originate from three different sources, the 32768hz oscillator, 32k_int oscillator or the system oscillator/4, the choice of which is determine by the f s clock source configuration option. note that the rtc interrupt period is controlled by both configuration options and an internal register rtcc. a configuration option selects the source clock for the in- ternal clock f s , and the rtcc register bits rt2, rt1 and rt0 select the division ratio. note that the actual divi- sion ratio can be programmed from 2 8 to 2 15 . essentially operating as a programmable timer, when the real time clock overflows it will set a real time clock interrupt flag which will in turn generate an inter - rupt request via the multi-function interrupt 1 vector. time base interrupt the time base interrupt is contained within the multi-function interrupt 1. for a time base interrupt to be generated, the global in - terrupt enable bit, emi,time base interrupt enable bit, etbi, and multi-function interrupt enable 1 bit, emf1i, must first be set. an actual time base interrupt will take place when the time base interrupt request flag, tbf, is set, a situation that will occur when the time base over - e e e ? # 2 0 . 6 7 c o 0 . 8 p 1 ( ) . f . 4 3 e . 4 . # e f . 4 3 # e . 4 5 rtc interrupt ht45r37 rev. 1.20 57 february 25, 2011 flows. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to the multi-function interrupt 1 vector at location18h, will take place. when the time base interrupt is serviced, the emi bit will be cleared to disable other interrupts, how - ever only the mf1f interrupt request flag will be reset. as the tbf flag will not be automatically reset, it has to be cleared by the application program. the purpose of the time base function is to provide an interrupt signal at fixed time periods. the time base in - terrupt clock source originates from the time base inter - rupt clock source originates from the internal clock source f s . this f s input clock first passes through a di - vider, the division ratio of which is selected by configura - tion options to provide longer time base interrupt periods. the time base interrupt time-out period ranges from 2 12 /f s ~2 15 /f s . the clock source that generates f s , which in turn controls the time base interrupt period, can originate from three different sources, the 32768hz oscillator, the 32k_int internal oscillator or the system oscillator/4, the choice of which is determine by the f s clock source configuration option. essentially operating as a programmable timer, when the time base overflows it will set a time base interrupt flag which will in turn generate an interrupt request via the multi-function interrupt 1 vector. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc0, intc1, mfic0 and mfic1 reg - isters until the corresponding interrupt is serviced or un - til the request flag is cleared by the application program. note that if a specific interrupt uses a multi-function in - terrupt vector then its interrupt request flag will not be automatically reset when the program enters the inter - rupt service routine. only the multi-function interrupt re - quest flag will be automatically reset. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the status or other registers are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. , , 6 5 $ & ( i $ & ( . 4 5 . 5 5 5 5 4 4 4 4 4 5 5 4 4 5 5 4 4 5 5 4 5 4 5 4 5 4 . # e . 9 # e . 4 5 # e . 4 4 # e . 4 . # e . 4 0 # e . 4 2 # e . 4 3 # e $ % & ( 4 @ 5 @ i * 4 @ 5 @ $ % & ( 4 @ % ) 5 @ ) 1 a g 5 g real time clock control register rtcc e e e ? # 2 0 . 6 7 c o 0 . 8 p 1 e ( ) . 4 . f . 4 3 e / . 4 . # e f . 4 3 # e time base interrupt ht45r37 rev. 1.20 58 february 25, 2011 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller . in this case, internal circuitry will ensure that the microcontroller ,af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller . all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller . as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. as the res pin is shared with an i/o pin its function must be selected using a configuration option. during this time delay, normal operation of the microcontroller will be inhib - ited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. ! & ( ( 5 ; 9 & ( ( ( power-on reset timing chart 5 # ! 5 ; 4 f 4 + 4 5 * f 4 5 5 * & ( ( & 5 ; 5 4 + k k & ( ( 4 1 2 4 2 k 0 5 5 k note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit ht45r37 rev. 1.20 59 february 25, 2011 res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. the res pin is shared with an i/o pin so its function must be first selected using a config - uration option. low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be selected using configuration options. the v lvr value will be selected as a pair in conjunction with a low voltage detect value. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack ( ( wdt time-out reset during normal operation timing chart ( wdt time-out reset during power down ! 5 ; 9 & ( ( 5 ; 2 & ( ( ( res reset timing chart $ & ( low voltage reset timing chart ht45r37 rev. 1.20 60 february 25, 2011 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. register reset (power-on) res reset (normal operation) wdt time-out (normal operation) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu rtcc 00 0111 00 0111 00 0111 uu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 11 1111 11 1111 11 1111 uu uuuu pbc 11 1111 11 1111 11 1111 uu uuuu pc 1 1111 1 1111 1 1111 u uuuu pcc 1 1111 1 1111 1 1111 u uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0l 0000 0 0000 0 0000 0 uuuu u pwm0h 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm1l 0000 0 0000 0 0000 0 uuuu u pwm1h 0000 0000 0000 0000 0000 0000 uuuu uuuu intc1 000 000 000 000 000 000 uuu uuu mfic0 00 00 00 00 00 00 uu uu mfic1 0000 0000 0000 0000 0000 0000 uuuu uuuu ascr0 1111 1111 1111 1111 1111 1111 uuuu uuuu ascr1 1111 1111 1111 1111 1111 1111 uuuu uuuu ascr2 1111 1111 1111 1111 1111 1111 uuuu uuuu adrl xxxx xxxx xxxx uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 10 000 10 000 10 000 uu uuu clkmod 0000 0x11 0000 0x11 0000 0x11 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu ht45r37 rev. 1.20 61 february 25, 2011 register reset (power-on) res reset (normal operation) wdt time-out (normal operation) wdt time-out (halt) papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu 00 0000 00 0000 00 0000 uu uuuu pcpu 0 000 0 000 0 000 u uuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu intedge 0000 0000 0000 uuuu misc 0000 1010 0000 1010 0000 1010 uuuu uuuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcoccr 0000 1 0000 1 0000 1 uuuu u tmrbh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 1xxx 00 1xxx 00 1xxx 00 uuuu uu simctl0 1110 000 1110 000 1110 000 uuuu uuu simctl1 1000 0001 1000 0001 1000 0001 uuuu uuuu simdr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simar /simctl2 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht45r37 rev. 1.20 62 february 25, 2011 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. five types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. system clock configurations there are six methods of generating the system clock, three high oscillators, two low oscillators and an exter - nally supplied clock. the three high oscillators are the external crystal/ceramic oscillator, internal rc oscillator and the external rc network. the two low oscillators are the fully integrated 32k_int oscillator and the external 32768hz oscillator. selecting whether the low or high oscillator is used as the system oscillator is imple - mented using the hlclk bit in the clkmod register. the source clock for the high and low oscillators is cho - sen via configuration options. the frequency of the slow oscillator is also determined using the slowc0~slowc2 bits in the clkmod register. system crystal/ceramic oscillator after selecting the external crystal configuration option, the simple connection of a crystal across osc1 and osc2, is normally all that is required to create the nec- essary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. in most applica - tions, resistor r1 is not required, however for those ap - plications where the lvr function is not used, r1 may be necessary to ensure the oscillator stops running when vdd falls below its operating range. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscil - lator pins. an additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1mhz, or low, which is defined as below 1 mhz. more information regarding oscillator applications is lo - cated on the holtek website. external system rc oscillator after selecting the correct configuration option, using the external system rc oscillator requires that a resis - tor, with a value between 47k and 1.5m ,iscon - nected between osc1 and vdd, and a 470pf capacitor is connected to ground. although this is a cost effective oscillator configuration, the oscillation frequency can vary with vdd, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are re - quired. for the value of the external resistor r osc refer to the appendix section for typical rc oscillator vs. temperature and vdd characteristics graphics. note that an internal capacitor together with the external resistor, r osc , are the components which determine the frequency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of oscillation. note that if this external system rc oscil - lation option is selected, as it requires osc1 external pin for its operation, the pc2/osc2 pin is free for use as normal i/o pin.the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. internal rc oscillator the internal rc oscillator is a fully integrated system os - cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz, the choice of which is indicated by the configuration options. note that if this internal system clock option is selected, as it requires no exter - nal pins for its operation, the osc1 and osc2 pins are free for use as normal i/o pins. refer to the appendix section for more information on the actual internal oscil - lator frequency vs. temperature and vdd characteris - tics graphics. . 4 . 4 4 crystal/ceramic oscillator 4 . 2 6 5 + & ( ( rc oscillator ht45r37 rev. 1.20 63 february 25, 2011 internal 32k_int oscillator when the device enters the sleep, slow or idle mode, its high frequency clock is switched off to reduce activity and to conserve power. however, in many microcontroller applications it may be necessary to keep some internal functions operational even when the microcontroller is in the power-down mode. to do this, the device has a 32k_int oscillator, which is a fully inte - grated free running rc oscillator with a typical period of 31.2 s at 5v, requiring no external components. it is se - lected via configuration option. external 32768hz oscillator with a function similar to the internal 32k-int 32khz os - cillator, that is to keep some device functions opera - tional during power down, this device also has an external 32768hz oscillator. this clock source has a fixed frequency of 32768hz and requires a 32768hz crystal to be connected between pins osc3 and osc4. the external resistor and capacitor components con- nected to the 32768hz crystal are not necessary to pro- vide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif- ferent crystal manufacturing tolerances. a configuration option selects whether the external 32768hz oscillator or the internal 32k_int oscillator is selected. selecting low frequency oscillators for use as a system oscillator is implmented using bits in the clkmod register. during power-up there is a time delay associated with the 32768hz oscillator waiting for it to start-up. to mini - mise this time delay, bit 4 of the rtcc register, known as the qosc bit, is provided to have a quick start-up function. during a power-up condition, this bit will be cleared to zero which will initiate the 32768hz oscillator quick start-up function. however, as there is additional power consumption associated with this quick start-up function, to reduce power consumption after start-up takes place, it is recommended that the application pro - gram should set the qosc bit high for about 2 seconds after power-on. it should be noted that, no matter what condition the qosc bit is set to, the 32768hz oscillator will always function normally, only there is more power consumption associated with the quick start-up function. note that if this external 32768hz oscillation option is not selected, the pc3/osc3 and pc4/osc4 pins are free for use as normal i/o pins. external oscillator the system clock can also be supplied by an externally supplied clock giving users a method of synchronising their external hardware to the microcontroller operation. this is selected using a configuration option and supply - ing the clock on pin osc1. note that if this external sys - tem clock option is selected, as it requires osc1 external pin for its operation, the pc2/osc2 pin is free for use as normal i/o pin. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin. system operating modes the devices have the ability to operate in several differ - ent modes. this range of operating modes, known as normal mode, slow mode, idle mode and sleep mode, allow the devices to run using a wide range of different slow and fast clock sources. the devices also possess the ability to dynamically switch between different clocks and operating modes. with this choice of operating functions, and a halt instruction, users are provided with a high degree of flexibility to ensure they obtain op- timal performance from the device, in terms of operating speed and power requirements. operating mode clock sources in discussing the system clocks for the devices, they can be seen as having a dual clock mode. these dual clocks are what are known as a high oscillator and the other as a low oscillator. the high and low oscillator are the system clock sources and can be selected dy - namically using the hlclk bit in the clkmod register. the high oscillator has the internal name f m whose source is selected using a configuration option from a choice of ei - ther an external crystal/resonator, external rc oscillator, internal rc oscillator or external clock source. the low oscillator clock source, has the internal name f sl , whose source is also selected by configuration op - tion from a choice of either an external 32768hz oscilla - tor or the internal 32k_int oscillator. this internal f sl ,f m clock, is further modified by the slowc0~slowc2 bits in the clkmod register to provide the low fre - quency clock source f slow . an additional sub internal clock, with the internal name f sub , is a 32khz clock source which can be sourced from either the internal 32k_int oscillator or an external 32768hz crystal, selected by configuration option. to - 2 0 . 4 4 0 . 6 7 c o 0 . 6 7 c o external 32768hz oscillator 0 . 8 p 1 e 0 . 8 internal 32k_int oscillator ht45r37 rev. 1.20 64 february 25, 2011 gether with f sys /4, it is used as a clock source for certain internal functions such as the watchdog timer, buzzer, rtc interrupt and time base interrupt. the internal clock f s , is simply a choice of either f sub or f sys /4, using a configuration option. operating modes after the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the clkmod register. a combination of the hlclk and idlen bits in the clkmod register and use of the halt instruction determine in which mode the device will be run. the devices can operate in the follow - ing modes. normal mode f m on, f slow on, f sys =f m , cpu on, f s on, f wdt on/off de - pending upon the wdt configuration option and wdt control register. slow mode0 f m off, f slow =32k_int oscillator or the 32768hz oscil - lator, f sys =f slow , cpu on, f s on, f wdt on/off depending upon the wdt configuration option and wdt control register. slow mode1 f m on, f slow =f m /2~f m /64, f sys =f slow , cpu on, f s on, f wdt on/off depending upon the wdt configuration option and wdt control register. idle mode f m ,f slow ,f sys off, cpu off; f sub on, f s on/off by selecting f sub or f sys /4, f wdt on/off depending upon the wdt configuration option and wdt control register. sleep mode f m ,f slow ,f sys ,f s , cpu off; f sub ,f wdt on/off depending upon the wdt configuration option and wdt control register. switching between modes the device switches between the different operating modes using a combination of the halt instruction and the idlen bit in the clkmod register. switching to one of the lower power modes enables the normal operating current to be reduced to a lower operating level or to a very low standby current level, a feature which is very important in low power battery applications. , $ + e ? 4 @ e 5 @ e $ 4 @ 5 @ c e 4 @ 5 @ $ % e 4 @ 5 @ # 4 @ 5 @ e $ 5 ( $ ! 1 c $ $ 8 c $ 6 $ 5 $ 4 $ . e $ e $ e $ e # 7 2 e # 0 . e # 4 7 e # e # 2 e # . $ . 5 5 5 5 4 4 4 4 $ 4 5 5 4 4 5 5 4 4 $ 5 5 4 5 4 5 4 5 4 ( $ ! . clock control register clkmod ht45r37 rev. 1.20 65 february 25, 2011 % " ' ) + % 8 % * c ' $ q g ( $ ! 1 g j 5 c ' $ q g ( $ ! 1 g j 4 % * % * c ' $ q g ( $ ! 1 g j 4 c ' $ q g ( $ ! 1 g j 5 % * g c $ 8 g g c $ $ 8 g 9 : 9 & ( 8 ! 5 ( ' ; ) 8 ' ; ) # % ( 8 % ( < = 5 ( ' ; ) 8 - = / > - ! ( > ( 9 ? 9 3 ! ! @ a % > " b ; < = = / > - ! ( > < e a 0 . 6 7 c o 0 . 8 p 1 a e ? j e ) & + % 8 e e e a 0 . 6 7 c o 0 . 8 p 1 k a e ? j e e 8 ) + % 8 e e e a 0 . 6 7 c o 0 . 8 p 1 a e ? j e e ) % 2 + % 8 e # e e a 0 . 6 7 c o 0 . 8 p 1 a e ? j e # . f e # 7 2 0 . 6 7 c o 0 . 8 p 1 r dual clock mode operation h e $ c $ $ 8 / e ? e h 0 . 6 7 c o e $ % * ! " 0 . 6 7 c o 0 . 8 p 1 e # . a ; ; ; e # 7 2 a e $ h h e e ? # 2 e / e e a / a / o o a ( 0 . 8 p 1 $ % 0 2 ! " ! " h ' $ h e c + , e c 4 4 . ! " * 4 e $ e / e $ 5 $ 4 $ . dual clock mode structure ht45r37 rev. 1.20 66 february 25, 2011 power down mode and wake-up executing the halt instruction if the device is running in the normal mode and the halt instruction is executed then the system clock will stop to conserve power. depending upon the condition of the idlen bit in the clkmod register, the system will enter either the sleep or idle mode. in these modes the system clock will stop running to conserve power, however as either the 32k_int or the external 32khz oscillator may continue to operate, certain internal func - tions may remain operational. when the halt instruction is executed in the normal mode, the following will occur: the system oscillator will stop running. the system will enter either the sleep or idle mode. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the 32k_int or external 32khz oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. this also applies to devices which have different package types, as there may be unbonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as out - puts. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup, using the pawu regis - ter, to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the pro- gram will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possi- ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe- cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the sleep or idle mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to t sst system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the t sst system clock period delay has ended. ht45r37 rev. 1.20 67 february 25, 2011 fast wake-up to minimise power consumption the device can enter the sleep or idle mode, where the clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the rtc or lirc oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabi - lised. as the clock source for the fast wake-up function is the watchdog timer clock, the watchdog timer must be enabled for this function to operate. if the watchdog timer is not enabled then the fast start-up function can - not be used. the fast wake-up enable/disable function is controlled using the configuration option. if the crystal oscillator is selected as the normal mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or rtc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 crystal clock cycles have elapsed, at which point the hto flag will switch high and the system will switch over to operating from the crystal oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 1~2 clock cycles of the erc, hirc or lirc to wake up the system from the sleep or idle mode. note that if the watchdog timer is disabled, which means that the rtc and lirc are all both off, then there will be no fast wake-up function available when the de- vice wakes-up from the sleep mode. low voltage detector lvd the low voltage detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the dc characteristics. lvd operation the lvd function must be first enabled via a configuration option after which bits 3 and 5 of the rtcc register are used to control the overall function of the lvd. bit 3 is the enable/disable control bit and is known as lvdc, when set low the overall function of the lvd will be disabled. bit 5 is the lvd detector output bit and is known as lvdo. under normal operation, and when the power supply voltage is above the specified vlvd value in the dc characteristic section, the lvdo bit will remain at a zero value. if the power supply voltage should fall below this vlvd value then the lvdo bit will change to a high value indicating a low voltage condi - tion. note that the lvdo bit is a read-only bit. by polling the lvdo bit in the rtcc register, the application pro - gram can therefore determine the presence of a low voltage condition. after power-on, or after a reset, the lvd will be switched off by clearing the lvdc bit in the rtcc register to zero. note that if the lvd is enabled there will be some power consumption associated with its internal circuitry, how - ever, by clearing the lvdc bit to zero the power can be minimised. it is important not to confuse the lvd with the lvr function. in the lvr function an automatic reset will be generated by the microcontroller , whereas in the lvd function only the lvdo bit will be affected with no influence on other microcontroller functions. there are a range of voltage values, selected using a configuration option, which can be chosen to activate the lvd. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the watchdog timer counter overflows. watchdog timer operation the watchdog timer clock source is provided by the in- ternal clock, f s , which is in turn supplied by one of two sources selected by configuration option: f sub or f sys /4. note that if the watchdog timer configuration option has been disabled, then any instruction relating to its op- eration will result in no operation. most of the watchdog timer options, such as en- able/disable, watchdog timer clock source and clear in- struction type are selected using configuration options. in addition to a configuration option to enable the watch - dog timer, there are four bits, wdten3~ wdten0, in the misc register to offer an additional enable control of the watchdog timer. these bits must be set to a specific value of 1010 to disable the watchdog timer. any other values for these bits will keep the watchdog timer en - abled. after power on these bits will have the disabled value of 1010. one of the wdt clock sources is the internal f sub , which can be sourced from either the 32k_int internal oscilla - tor or the 32768hz oscillator. the 32k_int internal os - cillator has an approximate period of 31.2 s at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with vdd, tem - perature and process variations. the 32768hz oscillator is supplied by an external 32768hz crystal. the other watchdog timer clock source option is the f sys /4 clock. whether the watchdog timer clock source is its own in - ternal 32k_int, the 32768hz oscillator or f sys /4, it is di - vided by 2 13 ~2 16 , using configuration option to obtain the required watchdog timer time-out period. the max time out period is when the 2 16 option is selected. this ht45r37 rev. 1.20 68 february 25, 2011 time-out period may vary with temperature, vdd and process variations. as the clear instruction only resets the last stage of the divider chain, for this reason the ac - tual division ratio and corresponding watchdog timer time-out can vary by a factor of two. the exact division ratio depends upon the residual value in the watchdog timer counter before the clear instruction is executed. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the power down mode, then the instruction clock is stopped and the watchdog timer will lose its protecting purposes. for systems that operate in noisy environ - ments, using the 32k_int rc oscillator is strongly rec - ommended. under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the power down mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. clearing the watchdog timer there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the watchdog timer. note that for this second op - tion, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no ef - fect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. ( e $ $ ( 4 + $ ( . + 4 . e ? # 2 0 . 8 p 1 ( ) e $ ( < . 4 0 # e a . 4 2 # e a . 4 3 # e . 4 7 # e = . 6 e # . e # . 4 . a e # . 4 0 a e # . 4 2 e # . 4 3 e watchdog timer + , 6 ( ! 1 5 5 ( ! 1 4 ' 5 f ' 0 ( % ! ( ! 5 ( ! 1 0 4 ( ! 1 . ( ! 1 0 ( ! 4 ( ! . ( ! 0 ( ! 1 . 5 ( ! 1 4 4 ( ! 1 5 5 ) watchdog timer software control misc ht45r37 rev. 1.20 69 february 25, 2011 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all options must be defined for proper system function, the details of which are shown in the table. no. options oscillator options 1 high frequency oscillator type selection 1. external crystal oscillator 2. external rc oscillator 3. internal rc oscillator 4. externally supplied clock 2 f sl and f sub clock selection (low frequency oscillator type selection) 1. 32768hz external oscillator 2. 32k_int internal oscillator 3 internal rc oscillator frequency select: 4mhz, 8mhz or 12mhz 4f s clock selection: f sub or f sys /4 5 xtal mode selection: 455khz or 1m~12mhz 6 fast wake-up from halt mode (only for external crystal oscillator): enable/disable reset option 7 rest pin function: pc0 or reset pin pfd options 8 pa3: normal i/o or pfd output 9 pfd clock selection: timer/event counter 0 or timer/event counter 1 buzzer options 10 pa0/pa1: normal i/o or bz/bz or pa0=bz and pa1 as normal i/o 11 buzzer frequency: f s /2 2 ,f s /2 3 ,f s /2 4 ,f s /2 5 ,f s /2 6 ,f s /2 7 ,f s /2 8 ,f s /2 9 time base option 12 time base time-out period: 2 12 /f s ,2 13 /f s ,2 14 /f s ,2 15 /f s watchdog options 13 watchdog timer function: enable or disable 14 clrwdt instructions: 1 or 2 instructions 15 wdt time-out period: 2 12 /f s ~2 13 /f s ,2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s ,2 15 /f s ~2 16 /f s lvd/lvr options 16 lvd function: enable or disable 17 lvr function: enable or disable 18 lvr/lvd voltage: 2.1v/2.2v or 3.15v/3.3v or 4.2v/4.4v spi options 19 sim interface enable/disable 20 spi_wcol: enable/disable 21 spi_csen: enable/disable, used to enable/disable (1/0) software csen function i 2 c option 22 i 2 c debounce time: no debounce, 1 system clock debounce, 2 system clock debounce application circuits c/r to f application circuit 1 c/r to f application circuit 2 ht45r37 rev. 1.20 70 february 25, 2011 / 5 # ' 1 5 f / 3 # ' 1 3 # 1 ! + ! + k 5 4 5 4 4 3 4 3 k 4 # 4 . # . # ) ) ' % # % ( 0 # 0 2 # 2 # ) ) ' % # % ( 5 # ! & ( ( & 5 ; 4 + & ( ( , # b 5 ; 4 f 4 + 4 5 * f 4 5 5 * 0 5 5 5 ; 5 4 + 4 1 2 4 2 / 5 # ' 1 5 f / 3 # ' 1 3 # 1 ! + ! + k 5 4 5 4 4 3 4 3 4 # 4 . # . # ) ) ' % # % ( 0 # 0 2 # 2 # ) ) ' % # % ( k 5 # ! & ( ( & 5 ; 4 + & ( ( , # b 5 ; 4 f 4 + 4 5 * f 4 5 5 * 0 5 5 5 ; 5 4 + 4 1 2 4 2 no. options timer/event counter and external interrupt pins filter option 23 interrupt and timer/event counter input pins internal filter on/off control applies to all pins c/r to f converter option 24 i/o pins or c/r to f converter inputs c/r to f application circuit 3 note: 1. the *r resistance and *c capacitance should be consideration for the frequency of rc osc. 2. r sensor 0~r sensor 15 are the resistance sensors. 3. c sensor 0~c sensor 15 are the capacitance sensors. ht45r37 rev. 1.20 71 february 25, 2011 / 5 # ' 1 5 f / 3 # ' 1 3 # 1 ! + ! + k 5 4 5 4 4 3 4 3 4 # 4 . # . # ) ) ' % # % ( 0 # 0 2 # 2 # ) ) ' % # % ( k 5 # ! & ( ( & 5 ; 4 + & ( ( , # b 5 ; 4 f 4 + 4 5 * f 4 5 5 * 0 5 5 5 ; 5 4 + 4 1 2 4 2 ht45r37 rev. 1.20 72 february 25, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for sub - traction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub- routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht45r37 rev. 1.20 73 february 25, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht45r37 rev. 1.20 74 february 25, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht45r37 rev. 1.20 75 february 25, 2011 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht45r37 rev. 1.20 76 february 25, 2011 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht45r37 rev. 1.20 77 february 25, 2011 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht45r37 rev. 1.20 78 february 25, 2011 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht45r37 rev. 1.20 79 february 25, 2011 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht45r37 rev. 1.20 80 february 25, 2011 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht45r37 rev. 1.20 81 february 25, 2011 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht45r37 rev. 1.20 82 february 25, 2011 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht45r37 rev. 1.20 83 february 25, 2011 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht45r37 rev. 1.20 84 february 25, 2011 package information 20-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.89 26.92 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht45r37 85 february 8, 2010 . 5 4 4 4 4 5 ' / ( ! + - c fig1. full lead packages . 5 4 4 4 4 5 ' / ( ! + - c fig2. 1 / 2 lead packages mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 0.945 0.985 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.00 25.02 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 ht45r37 86 february 8, 2010 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.496 0.512 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 12.60 13.00 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 08 ht45r37 rev. 1.20 87 february 25, 2011 . 5 4 4 4 4 5 ' / ( ! + m - c 24-pin skdip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 1.230 1.280 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 31.24 32.51 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht45r37 rev. 1.20 88 february 25, 2011 . 2 4 4 0 4 . ' / ( ! + - c fig1. full lead packages . 2 4 4 0 4 . ' / ( ! + - c fig2. 1 / 2 lead packages ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.46 30.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht45r37 rev. 1.20 89 february 25, 2011 mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.08 30.10 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 ht45r37 rev. 1.20 90 february 25, 2011 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 08 ht45r37 rev. 1.20 91 february 25, 2011 . 2 4 4 0 4 . ' / ( ! + m - c 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 1.395 b 0.278 0.298 c 0.125 0.135 d 0.125 0.145 e 0.016 0.020 f 0.050 0.070 g 0.100 h 0.295 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 34.93 35.43 b 7.06 7.57 c 3.18 3.43 d 3.18 3.68 e 0.41 0.51 f 1.27 1.78 g 2.54 h 7.49 8.00 i 9.53 ht45r37 rev. 1.20 92 february 25, 2011 . 4 4 3 4 2 ' / ( ! + - c 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 08 ht45r37 rev. 1.20 93 february 25, 2011 . 4 4 3 4 2 ' / ( + m - c ! 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 08 ht45r37 rev. 1.20 94 february 25, 2011 . 4 4 3 4 2 ' / ( + m - c ! saw type 32-pin (5mm 5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028 0.031 a1 0.000 0.002 a3 0.008 b 0.007 0.012 d 0.197 e 0.197 e 0.020 d2 0.049 0.128 e2 0.049 0.128 l 0.012 0.020 k symbol dimensions in mm min. nom. max. a 0.70 0.80 a1 0.00 0.05 a3 0.20 b 0.18 0.30 d 5.00 e 5.00 e 0.50 d2 1.25 3.25 e2 1.25 3.25 l 0.30 0.50 k ht45r37 rev. 1.20 95 february 25, 2011 ( ! ' 4 ' 0 ' ( . $ ! . 8 4 9 4 7 4 6 . 2 . 3 0 . product tape and reel specifications reel dimensions sop 20w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 sop 24w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ht45r37 rev. 1.20 96 february 25, 2011 ' / 4 . ( sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 saw type qfn 32-pin (5mm 5mm) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.5 +0.3/-0.2 t2 reel thickness ht45r37 rev. 1.20 97 february 25, 2011 carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 sop 24w symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.90.1 b0 cavity width 15.90.1 k0 cavity depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width 21.30.1 ht45r37 rev. 1.20 98 february 25, 2011 ( 4 4 5 ( ! + 8 5 / 5 ' 5 * 4 ; c sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht45r37 rev. 1.20 99 february 25, 2011 ht45r37 rev. 1.20 100 february 25, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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